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74HC4017PW - Johnson decade counter

Download the 74HC4017PW datasheet PDF. This datasheet also covers the 74HC4017 variant, as both devices belong to the same johnson decade counter family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded outputs (Q0 to Q9), an output from the most significant flip-flop (Q5-9), two clock inputs (CP0 and CP1) and an overriding asynchronous master reset input (MR).

Key Features

  • Wide supply voltage range from 2.0 V to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standards:.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0 V to 6.0 V).
  • Input levels:.
  • For 74HC4017: CMOS level.
  • For 74HCT4017: TTL level.
  • ESD protection:.
  • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V.
  • CD.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC4017-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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74HC4017 Johnson decade counter NXP
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74HC40103 8-bit synchronous binary down counter NXP
74HC40104 4-bit bidirectional universal shift register Philips

Other Datasheets by Nexperia

Part Number Description
74HC4017 Johnson decade counter
74HC4017-Q100 Johnson decade counter
74HC4017BQ Johnson decade counter
74HC4017D Johnson decade counter
74HC4017DB Johnson decade counter

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC4017; 74HCT4017 Johnson decade counter with 10 decoded outputs Rev. 8 — 27 March 2024 Product data sheet 1. General description The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded outputs (Q0 to Q9), an output from the most significant flip-flop (Q5-9), two clock inputs (CP0 and CP1) and an overriding asynchronous master reset input (MR). The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or a HIGH-to-LOW transition at CP1 while CP0 is HIGH. When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5, 6, 7, 8 and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW) independent of the clock inputs (CP0 and CP1).