Nexperia 74HC73
The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.| Part No. | 74HC73 |
|---|---|
| Datasheet | 74HC73 Download |
| Manufacturer |  Nexperia |
| Description | Dual JK flip-flop |
| Buy | Stock & Price |
FEATURES AND BENEFITS
● CMOS low-power dissipation● Wide supply voltage range from 2.0 to 6.0 V
● High noise immunity
● Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
● Complies with JEDEC standards
● JESD8C (2.7 V to 3.6 V)
● JESD7A (2.0 V to 6.0 V)
● ESD protection:
● HBM JESD22-A114F exceeds 2000 V
● MM JESD22-A115-A exceeds 200 V
● Specified from -40 °C to +80 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74HC73D -40 °C to +125 °C 74HC73PW -40 °C to +125 °C Name SO14 TSSOP14
DESCRIPTION
plastic small outline package; 14 leads; body width 3.9 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT108-1 SOT402-1 Nexperia 4. Functional diagram 74HC73 Dual JK flip-flop with reset; negative-edge trigger 14 1J 1 1CP J Q FF1 CP 1Q 12 3 1K 2 1R K Q R 1Q 13 7 2J 5 2CP J Q FF2 CP 2Q 9 10 2K 6 2R K Q R 2Q 8 001aab981 Fig. 1. Functional diagram 14 1J 7 2J 1 1CP 5 2CP 3 1K 10 2K J FF CP K R Q 1Q 2Q 12 9 Q 1Q 13 2Q 8 1R 2R 26 001aab979 Fig.
