Datasheet4U Logo Datasheet4U.com

74HC73 - Dual JK flip-flop

General Description

The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs.

The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.

Key Features

  • CMOS low-power dissipation.
  • Wide supply voltage range from 2.0 to 6.0 V.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standards.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0 V to 6.0 V).
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • Specified from -40 °C to +80 °C and from -40 °C to +125 °C 3. Ordering infor.

📥 Download Datasheet

Datasheet Details

Part number 74HC73
Manufacturer Nexperia
File Size 240.61 KB
Description Dual JK flip-flop
Datasheet download datasheet 74HC73 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74HC73 Dual JK flip-flop NXP
74HC7014 Hex non-inverting precision Schmitt-trigger Philips
74HC7030 9-bit x 64-word FIFO register Philips
74HC7046A Phase-locked-loop Philips
74HC7080 16-bit even/odd parity generator/checker Philips

Other Datasheets by Nexperia

Part Number Description
74HC73D Dual JK flip-flop
74HC7014 Hex non-inverting precision Schmitt-trigger
74HC7014-Q100 Hex non-inverting precision Schmitt-trigger
74HC7014D Hex non-inverting precision Schmitt-trigger
74HC74 Dual D-type flip-flop

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC73 Dual JK flip-flop with reset; negative-edge trigger Rev. 7 — 13 September 2021 Product data sheet 1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2.