Nexperia 74HC75D
The 74HC75 is a quad bistable transparent latch with complementary outputs. When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs (nD) as long as LEnn is HIGH (transparent).FEATURES AND BENEFITS
● Wide supply voltage range from 2.0 V to 6.0 V● CMOS low power dissipation
● High noise immunity
● Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
● Complies with JEDEC standards:
● JESD8C (2.7 V to 3.6 V)
● JESD7A (2.0 V to 6.0 V)
● Complementary Q and Q outputs
● VCC and GND on the center pins
● CMOS input levels
● ESD protection:
● HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
● CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
● Specified from -40 °C to +85 °C and from -40 °C to +125 °C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74HC75D -40 °C to +125 °C Name SO16 74HC75PW -40 °C to +125 °C TSSOP16
DESCRIPTION
Version plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm Nexperia 4. Functional diagram 13 LE12 2 1D 1Q 16 1Q 1 3 2D 2Q 15 2Q 14 L1,2 6 L3,4 3Q 3D 3Q 10 11 7 4D 4Q 9 4Q 8 LE34 4 001aab851 Fig.