74HCT107 Datasheet | Nexperia

description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and plementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits - Wide supply voltage range from 2.0 V to 6.0 V - CMOS low power dissipation - High noise immunity - Latch-up performance exceeds 100 m A per JESD 78 Class II Level B - plies with JEDEC standards: - JESD8C (2.7 V to 3.6 V) - JESD7A (2.0 V to 6.0 V) - Input levels: - The 74HC107: CMOS levels - The 74HCT107: TTL levels - ESD protection: - HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V - CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V - Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74HC107D 74HCT107D -40 °C to +125 °C SO14 74HC107PW -40 °C to +125 °C TSSOP14 Description plastic small outline package; 14 leads; body width 3.9 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT108-1 SOT402-1 Nexperia 4. Functional diagram 1 8 1J 2J Q 1Q 3 2Q 5 12 1CP 9 2CP 4 11 1K 2K Q 1Q 2 2Q...