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74HCT112 - Dual JK flip-flop

This page provides the datasheet information for the 74HCT112, a member of the 74HC112 Dual JK flip-flop family.

Datasheet Summary

Description

The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop.

Features

  • Input levels:.
  • For 74HC112: CMOS level.
  • For 74HCT112: TTL level.
  • Asynchronous set and reset.
  • Specified in compliance with JEDEC standard no. 7A.
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74HC112D -40 °C to +125 °C 74HCT11.

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Datasheet preview – 74HCT112

Datasheet Details

Part number 74HCT112
Manufacturer nexperia
File Size 262.50 KB
Description Dual JK flip-flop
Datasheet download datasheet 74HCT112 Datasheet
Additional preview pages of the 74HCT112 datasheet.

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Full PDF Text Transcription

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74HC112; 74HCT112 Dual JK flip-flop with set and reset; negative-edge trigger Rev. 4 — 11 January 2021 Product data sheet 1. General description The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
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