Datasheet4U Logo Datasheet4U.com

74HCT1G02 - 2-input NOR gate

Download the 74HCT1G02 datasheet PDF. This datasheet also covers the 74HC1G02 variant, as both devices belong to the same 2-input nor gate family and are provided as variant models within a single manufacturer datasheet.

General Description

The74HC1G02; 74HCT1G02 is a single 2-input NOR gate.

Inputs include clamp diodes.

This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Key Features

  • Wide supply voltage range from 2.0 V to 6.0 V.
  • CMOS low power dissipation.
  • Symmetrical output impedance.
  • High noise immunity.
  • Balanced propagation delays.
  • Input levels:.
  • For 74HC1G02: CMOS level.
  • For 74HCT1G02: TTL level.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standards:.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0 V to 6.0 V).
  • ESD protecti.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC1G02-nexperia.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC1G02; 74HCT1G02 2-input NOR gate Rev. 5 — 21 January 2022 Product data sheet 1. General description The74HC1G02; 74HCT1G02 is a single 2-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • Wide supply voltage range from 2.0 V to 6.0 V • CMOS low power dissipation • Symmetrical output impedance • High noise immunity • Balanced propagation delays • Input levels: • For 74HC1G02: CMOS level • For 74HCT1G02: TTL level • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2.0 V to 6.