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74LV02APW Datasheet PDF

Nexperia 74LV02APW

The 74LV02A is a quad 2-input NOR gate. This feature allows the use of these devices as translators in mixed voltage environments. This device is fully specified for partial power down applications using IOFF.
Part No. 74LV02APW
Datasheet 74LV02APW Download
Manufacturer
Nexperia
Description Quad 2-input NOR gate
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74LV02APW datasheet page 1 preview

FEATURES AND BENEFITS

● Wide supply voltage range from 2.0 V to 5.5 V
● Maximum tpd of 10 ns at 5 V
● Typical VOL(p) < 0.8 V at VCC = 3.3 V, Tamb = 25 °C
● Typical VOH(v) > 2.3 V at VCC = 3.3 V, Tamb = 25 °C
● Supports mixed-mode voltage operation on all ports
● IOFF circuitry provides partial Power-down mode operation
● Latch-up performance exceeds 250 mA per JESD 78 Class II
● ESD protection:
● MM: MM JESD22-A115-B exceeds 200 V
● HBM: ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 4 kV
● CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 2 kV
● Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74LV02APW -40 °C to +125 °C Name TSSOP14

DESCRIPTION

plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT402-1 Nexperia 4. Functional diagram 2 1 1 3 2 1A 3 1B 5 2A 6 2B 8 3A 9 3B 11 4A 12 4B 1Y 1 2Y 4 3Y 10 4Y 13 mna216 Fig. 1. Logic symbol 5 1 4 6 8 1 10 9 11 1 13 12 mna217 Fig.
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