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74LV4094D - 8-stage shift-and-store bus register

This page provides the datasheet information for the 74LV4094D, a member of the 74LV4094 8-stage shift-and-store bus register family.

Description

The 74LV4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs.

Both the shift and storage register have separate clocks.

Features

  • Optimized for low voltage.

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Datasheet preview – 74LV4094D

Datasheet Details

Part number 74LV4094D
Manufacturer nexperia
File Size 277.88 KB
Description 8-stage shift-and-store bus register
Datasheet download datasheet 74LV4094D Datasheet
Additional preview pages of the 74LV4094D datasheet.

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Full PDF Text Transcription

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74LV4094 8-stage shift-and-store bus register Rev. 8 — 18 March 2021 Product data sheet 1. General description The 74LV4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is HIGH.
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