Datasheet4U Logo Datasheet4U.com

74LVC163 - Presettable synchronous 4-bit binary counter

Description

The 74LVC163 is a synchronous presettable binary counter which

Features

  • Wide supply voltage range from 1.2 V to 3.6 V.
  • Inputs accept voltages up to 5.5 V.
  • CMOS low power consumption.
  • Direct interface with TTL levels.
  • Synchronous reset.
  • Synchronous counting and loading.
  • Two count enable inputs for n-bit cascading.
  • Positive edge-triggered clock.
  • Complies with JEDEC standard:.
  • JESD8-7A (1.65 V to 1.95 V).
  • JESD8-5A (2.3 V to 2.7 V).
  • JESD8-C/JESD36 (2.7 V to 3.6 V.

📥 Download Datasheet

Datasheet preview – 74LVC163

Datasheet Details

Part number 74LVC163
Manufacturer nexperia
File Size 290.83 KB
Description Presettable synchronous 4-bit binary counter
Datasheet download datasheet 74LVC163 Datasheet
Additional preview pages of the 74LVC163 datasheet.

📁 Similar Datasheet

  • 74LVC163 - Presettable synchronous 4-bit binary counter (Philips)
  • 74LVC16374A - 16-bit edge triggered D-type flip-flop (Philips)
  • 74LVC161 - Presettable synchronous 4-bit binary counter (Philips)
  • 74LVC161284 - 19-BIT BUS INTERFACE (Texas Instruments)
  • 74LVC161284 - LOW VOLTAGE HIGH SPEED IEEE1284 TRANSCEIVER (ST Microelectronics)
  • 74LVC162245A - 16-bit transceiver (Philips)
  • 74LVC162373A - 16-bit D-type transparent latch (Philips)
  • 74LVC162374A - 16-bit edge triggered D-type flip-flop (Philips)
  • 74LVC16240A - 16-bit buffer/line driver (Philips)
  • 74LVC16244A - 16-bit buffer/line driver (NXP Semiconductors)
Other Datasheets by nexperia

Full PDF Text Transcription

Click to expand full text
74LVC163 Presettable synchronous 4-bit binary counter; synchronous reset Rev. 7 — 19 April 2021 Product data sheet 1. General description The 74LVC163 is a synchronous presettable binary counter which features an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (pin CP). The outputs (pins Q0 to Q3) of the counters may be preset to a HIGH-level or LOW-level. A LOW-level at the parallel enable input (pin PE) disables the counting action and causes the data at the data inputs (pins D0 to D3) to be loaded into the counter on the positive-going edge of the clock (provided that the set-up and hold time requirements for PE are met).
Published: |