74LVC1G08GW
description
The 74LVC1G08 is a single 2-input AND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall time.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
2. Features and benefits
- Wide supply voltage range from 1.65 V to 5.5 V
- High noise immunity
- ±24 m A output drive (VCC = 3.0 V)
- CMOS low power dissipation
- Direct interface with TTL levels
- Overvoltage tolerant inputs to 5.5 V
- IOFF circuitry provides partial Power-down mode operation
- Latch-up performance ≤ 250 m A
- plies with JEDEC standard:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8C (2.7 V to 3.6 V)
- JESD36 (4.5 V to 5.5 V)
- ESD protection:
-...
