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74LVCH16374A - 16-bit edge-triggered D-type flip-flop

Download the 74LVCH16374A datasheet PDF. This datasheet also covers the 74LVC16374A variant, as both devices belong to the same 16-bit edge-triggered d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74LVC16374A; 74LVCH16374A is a 16-bit edge-triggered D-type flip-flop with 3-state outputs.

The device can be used as two 8-bit flip-flops or one 16-bit flip-flop.

Key Features

  • Overvoltage tolerant inputs to 5.5 V.
  • Wide supply voltage range from 1.2 V to 3.6 V.
  • CMOS low power dissipation.
  • Multibyte flow-through standard pinout architecture.
  • Low inductance multiple supply pins for minimum noise and ground bounce.
  • Direct interface with TTL levels.
  • All data inputs have bus hold (74LVCH16374A only).
  • High-impedance outputs when VCC = 0 V.
  • IOFF circuitry provides partial Power-down mode operati.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74LVC16374A-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74LVCH16374A
Manufacturer Nexperia
File Size 237.37 KB
Description 16-bit edge-triggered D-type flip-flop
Datasheet download datasheet 74LVCH16374A Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74LVC16374A; 74LVCH16374A 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state Rev. 13 — 27 September 2021 Product data sheet 1. General description The 74LVC16374A; 74LVCH16374A is a 16-bit edge-triggered D-type flip-flop with 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. The device features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8-bits. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices.