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74LVTH16374A - 16-bit edge-triggered D-type flip-flop

Download the 74LVTH16374A datasheet PDF. This datasheet also covers the 74LVT16374A variant, as both devices belong to the same 16-bit edge-triggered d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74LVT16374A; 74LVTH16374A is a 16-bit edge-triggered D-type flip-flop with 3-state outputs.

The device can be used as two 8-bit flip-flops or one 16-bit flip-flop.

Key Features

  • 16-bit edge-triggered flip-flop.
  • 3-state buffers.
  • Output capability: +64 mA and -32 mA.
  • Wide supply voltage range from 2.7 to 3.6 V.
  • Overvoltage tolerant inputs to 5.5 V.
  • BiCMOS high speed and output drive.
  • Direct interface with TTL levels.
  • Input and output interface capability to systems at 5 V supply.
  • Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs. (74LVTH16374A only).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74LVT16374A-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74LVTH16374A
Manufacturer Nexperia
File Size 228.89 KB
Description 16-bit edge-triggered D-type flip-flop
Datasheet download datasheet 74LVTH16374A Datasheet

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Other Datasheets by Nexperia

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74LVTH16244B 16-bit buffer/driver
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state Rev. 12 — 6 August 2021 Product data sheet 1. General description The 74LVT16374A; 74LVTH16374A is a 16-bit edge-triggered D-type flip-flop with 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. The device features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8-bits. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops. 2.