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74VHC595-Q100 - 8-bit serial-in/serial-out or parallel-out shift register

General Description

The 74VHC595-Q100; 74VHCT595-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL).

It is specified in compliance with JEDEC standard No.

7A.

Key Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C.
  • Balanced propagation delays.
  • All inputs have Schmitt-trigger action.
  • Inputs accept voltages higher than VCC.
  • Input levels:.
  • For 74VHC595-Q100: CMOS level.
  • For 74VHCT595-Q100: TTL level.
  • ESD protection:.
  • MIL-STD-883, method 3015 exceeds 2000 V.
  • HBM JESD22-A114F exceeds.

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Datasheet Details

Part number 74VHC595-Q100
Manufacturer Nexperia
File Size 297.43 KB
Description 8-bit serial-in/serial-out or parallel-out shift register
Datasheet download datasheet 74VHC595-Q100 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74VHC595-Q100; 74VHCT595-Q100 8-bit serial-in/serial-out or parallel-out shift register with output latches Rev. 2 — 25 June 2020 Product data sheet 1. General description The 74VHC595-Q100; 74VHCT595-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. The 74VHC595-Q100; 74VHCT595-Q100 are 8-stage serial shift registers with a storage register and 3-state outputs. The shift registers have separate clocks. Data is shifted on the positive-going transitions of the shift register clock input (SHCP). The data in each register is transferred to the storage register on a positive-going transition of the storage register clock input (STCP).