Datasheet4U Logo Datasheet4U.com

HEF4017B-Q100 - 5-stage Johnson decade counter

General Description

The HEF4017B-Q100 is a 5-stage Johnson decade counter with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q5-9), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR).

Key Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from 40 C to +85 C and from 40 C to +125 C.
  • Automatic counter correction.
  • Tolerant of slow clock rise and fall times.
  • Fully static operation.
  • 5 V, 10 V, and 15 V parametric ratings.
  • Standardized symmetrical output characteristics.
  • ESD protection:.
  • MIL-STD-833, method 3015 exceeds 2000 V.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V (C.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
HEF4017B 5-stage Johnson decade counter NXP
HEF4017B 5-stage Johnson counter Philips
HEF40174B Hex D-type flip-flop NXP
HEF40175B Quadruple D-type flip-flop NXP
HEF40106B Hex inverting Schmitt trigger NXP

Other Datasheets by Nexperia

Part Number Description
HEF4017B 5-stage Johnson decade counter
HEF40175B Quad D-type flip-flop
HEF40106B Hex inverting Schmitt trigger
HEF40106B-Q100 Hex inverting Schmitt trigger
HEF4011B Quad 2-input NAND gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HEF4017B-Q100 5-stage Johnson decade counter Rev. 1 — 4 June 2014 Product data sheet 1. General description The HEF4017B-Q100 is a 5-stage Johnson decade counter with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q5-9), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR). The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or a HIGH-to-LOW transition at CP1 while CP0 is HIGH (see Table 3). When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5, 6, 7, 8, and 9, can be used to drive the CP0 input of the next counter.