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HEF4027B-Q100 - Dual JK flip-flop

General Description

The HEF4027B-Q100 is a dual positive-edge triggered JK flip-flop featuring independent set direct (nSD), clear direct (nCD), clock inputs (nCP) and complementary outputs (nQ and nQ).

Data is accepted when nCP is LOW, and transferred to the output on the positive-going edge of the clock.

Key Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 3).
  • Specified from -40 °C to +85 °C.
  • Wide supply voltage range from 3.0 V to 15.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Fully static operation.
  • 5 V, 10 V, and 15 V parametric ratings.
  • Standardized symmetrical output characteristics.
  • Complies with JEDEC standard JESD 13-B.
  • ESD protection:.
  • HBM: ANSI/ESDA/JEDEC JS-001.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HEF4027B-Q100 Dual JK flip-flop Rev. 3 — 8 August 2024 Product data sheet 1. General description The HEF4027B-Q100 is a dual positive-edge triggered JK flip-flop featuring independent set direct (nSD), clear direct (nCD), clock inputs (nCP) and complementary outputs (nQ and nQ). Data is accepted when nCP is LOW, and transferred to the output on the positive-going edge of the clock. The asynchronous clear-direct (nCD) and set-direct (nSD) are independent and override the nJ, nK, and nCP inputs. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD.