Datasheet4U Logo Datasheet4U.com

HEF4094BT - 8-stage shift-and-store register

This page provides the datasheet information for the HEF4094BT, a member of the HEF4094B 8-stage shift-and-store register family.

Description

The HEF4094B is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs.

Both the shift and storage register have separate clocks.

Features

  • Fully static operation.
  • 5 V, 10 V, and 15 V parametric ratings.
  • Wide supply voltage range from 3.0 V to 15.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Standardized symmetrical output characteristics.
  • Complies with JEDEC standard JESD 13-B.
  • ESD protection:.
  • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V.
  • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V.
  • Specified from -40 °C to +85.

📥 Download Datasheet

Datasheet preview – HEF4094BT

Datasheet Details

Part number HEF4094BT
Manufacturer nexperia
File Size 260.71 KB
Description 8-stage shift-and-store register
Datasheet download datasheet HEF4094BT Datasheet
Additional preview pages of the HEF4094BT datasheet.

📁 Similar Datasheet

  • HEF4094B - 8-stage shift-and-store register (NXP)
  • HEF4094B - 8-stage shift-and-store bus register (Philips)
  • HEF4094B-Q100 - 8-stage shift-and-store register (NXP)
  • HEF4093B - Quad 2-input NAND Schmitt trigger (NXP)
  • HEF4093B - Quadruple 2-input NAND Schmitt trigger (Philips)
  • HEF4000B - Dual 3-input NOR gate and inverter (NXP)
  • HEF4001B - Quadruple 2-input NOR gate (NXP)
  • HEF4001B - Quadruple 2-input NOR gate (Philips)
  • HEF4001UB - Quadruple 2-input NOR gate (NXP)
  • HEF4002B - Dual 4-input NOR gate (NXP)
Other Datasheets by nexperia

Full PDF Text Transcription

Click to expand full text
HEF4094B 8-stage shift-and-store register Rev. 15 — 5 September 2024 Product data sheet 1. General description The HEF4094B is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is HIGH.
Published: |