DESCRIPTION
A EEPROM Serial 2k−bit I2C memory and a system power supervisor with brown−out protection are integrated together in low power CMOS technology. Memory interface is via a 400 kHz I2C bus. The CAT1021 also has a Write Protect input (WP). Write operations are disabled if WP is connected to a logic high. MSOP−8 CASE 846AD TDFN−8 CASE 511AL All supervisors have a 1.6 second watchdog timer circuit that resets a system to a known state if software or a hardware glitch halts or “hangs” the system. For the CAT1021 and CAT1022, the watchdog ORDERING INFORMATION timer monitors the SDA signal. The CAT1023 has a separate watchdog timer interrupt input pin, WDI. For Ordering Information details, see page 13. The power supply monitor and reset circuit protect memory and system controllers during power up/down and against brownout conditions. Five reset threshold voltages support 5 V, 3.3 V and 3 V systems. If power supply voltages are out of tolerance reset signals become active, preventing the system microcontroller, ASIC or peripherals from operating.
onsemi
