DESCRIPTION
ESD protection for the video, DDC and SYNC lines is implemented with low−capacitance current steering diodes. All connector interface pins are designed to safely handle the high current spikes specified by IEC−61000−4−2 Level 4 (±8 kV contact discharge). Separate positive supply rails are provided for the VIDEO / SYNC signals and DDC signals to facilitate interfacing with low voltage video controller ICs and microcontrollers to provide design flexibility in multi−supply−voltage environments. Two Schmitt−triggered non−inverting buffers redrive and condition the HSYNC and VSYNC signals from the video connector (SYNC1, SYNC2). These buffers accept VESA VSIS compliant TTL input signals and convert them to CMOS output levels that swing between ground and VCC. Two N−channel MOSFETs provide the level shifting function required when the DDC controller or EDID EEPROM is operated at a lower supply voltage than the monitor. The gate terminals for these MOSFETS (VCC_DDC) should be connected to the supply rail (typically 3.3 V, 2.5 V, etc.) that supplies power to the transceivers of the DDC controller.
onsemi
