DESCRIPTION
The LS164 is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B); either of these inputs can be used as an active HIGH Enable for data entry through the other input. An unused input must be tied HIGH, or both inputs connected together. Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right and enters into Q0 the logical AND of the two data inputs (A●B) that existed before the rising clock edge. A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all Q outputs LOW. MODE SELECT — TRUTH TABLE OPERATING MODE INPUTS MR A B OUTPUTS Q0 Q1−Q7 Reset (Clear) L X X L L−L Shift H I I L q0 − q6 H I h L q0 − q6 H h I L q0 − q6 H h h H q0 − q6 L (l) = LOW Voltage Levels H (h) = HIGH Voltage Levels X = Don’t Care qn = Lower case letters indicate the state of the referenced input or output one qn = set-up time prior to the LOW to HIGH clock transition.
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