www.Datasheet4U.com

74ABT16841A Datasheet
20-bit bus interface latch

No Preview Available !

74ABT16841A pdf
Download PDF File

INTEGRATED CIRCUITS
74ABT16841A
20-bit bus interface latch (3-State)
Product data
Replaces data sheet 74ABT16841A/74ABTH16841A of 2002 Dec 17
2004 Feb 02
Philips
Semiconductors


74ABT16841A Datasheet
20-bit bus interface latch

No Preview Available !

74ABT16841A pdf
Download PDF File

Philips Semiconductors
20-bit bus interface latch (3-State)
Product data
74ABT16841A
FEATURES
High speed parallel latches
Live insertion/extraction permitted
Extra data width for wide address/data paths or buses carrying
parity
Power-up 3-State
Power-up reset
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
Output capability: +64 mA / –32 mA
Latch-up protection exceeds 500 mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT16841A Bus interface latch is designed to provide extra
data width for wider data/address paths of buses carrying parity.
The 74ABT16841A consists of two sets of ten D-type latches with
3-State outputs. The flip-flops appear transparent to the data when
Latch Enable (nLE) is HIGH. This allows asynchronous operation,
as the output transition follows the data in transition. On the nLE
HIGH-to-LOW transition, the data that meets the set-up and hold
time is latched.
Data appears on the bus when the Output Enable (nOE) is LOW.
When nOE is HIGH the output is in the high-impedance state.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
CIN
COUT
ICCZ
ICCL
Propagation delay
nDx to nQx
Input capacitance
Output capacitance
Quiescent supply current
CONDITIONS
Tamb = 25 °C; GND = 0 V
CL = 50 pF; VCC = 5 V
VI = 0 V or VCC
VO = 0 V or VCC; 3-State
Outputs disabled; VCC = 5.5 V
Outputs LOW; VCC = 5.5 V
ORDERING INFORMATION
Tamb = –40 °C to +85 °C
Type number
Package
Name
74ABT16841ADL
SSOP56
74ABT16841ADGG TSSOP56
Description
plastic shrink small outline package; 56 leads; body width 7.5 mm
plastic thin shrink small outline package; 56 leads; body width 6.1 mm
TYPICAL UNIT
3.1
2.2
ns
4 pF
7 pF
500 µA
10 mA
Version
SOT371-1
SOT364-1
PIN DESCRIPTION
PIN NUMBER
55, 54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
2, 3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
1, 28
56, 29
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
SYMBOL
1D0 – 1D9
2D0 – 2D9
1Q0 – 1Q9
2Q0 – 2Q9
1OE, 2OE
1LE, 2LE
GND
VCC
Data inputs
FUNCTION
Data outputs
Output enable inputs (active-LOW)
Latch enable inputs (active rising edge)
Ground (0 V)
Positive supply voltage
2004 Feb 02
2


74ABT16841A Datasheet
20-bit bus interface latch

No Preview Available !

74ABT16841A pdf
Download PDF File

Philips Semiconductors
20-bit bus interface latch (3-State)
Product data
74ABT16841A
PIN CONFIGURATION
1OE 1
1Q0 2
1Q1 3
GND 4
1Q2 5
1Q3 6
VCC 7
1Q4 8
1Q5 9
1Q6 10
GND 11
1Q7 12
1Q8 13
1Q9 14
2Q0 15
2Q1 16
2Q2 17
GND 18
2Q3 19
2Q4 20
2Q5 21
VCC 22
2Q6 23
2Q7 24
GND 25
2Q8 26
2Q9 27
2OE 28
56 1LE
55 1D0
54 1D1
53 GND
52 1D2
51 1D3
50 VCC
49 1D4
48 1D5
47 1D6
46 GND
45 1D7
44 1D8
43 1D9
42 2D0
41 2D1
40 2D2
39 GND
38 2D3
37 2D4
36 2D5
35 VCC
34 2D6
33 2D7
32 GND
31 2D8
30 2D9
29 2LE
SA00076
LOGIC SYMBOL
55 54 52 51 49 48 47 45 44 43
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9
56 1LE
1 1OE
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9
2 3 5 6 8 9 10 12 13 14
42 41 40 38 37 36 34 33 31 30
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9
29 2LE
28 2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
15 16 17 19 20 21 23 24 26 27
SH00023
2004 Feb 02
LOGIC SYMBOL (IEEE/IEC)
1OE
1LE
2OE
2LE
1
56
28
29
1D0 55
1D1 54
1D2 52
1D3 51
1D4 49
1D5 48
1D6 47
1D7 45
1D8 44
1D9 43
2D0 42
2D1 41
2D2 40
2D3 38
2D4 37
2D5 36
2D6 34
2D7 33
2D8 31
2D9 30
EN2
C1
EN4
C3
1D
2
3D 4
2 1Q0
3 1Q1
5 1Q2
6 1Q3
8 1Q4
9 1Q5
10 1Q6
12 1Q7
13 1Q8
14 1Q9
15 2Q0
16 2Q1
17 2Q2
19 2Q3
20 2Q4
21 2Q5
23 2Q6
24 2Q7
26 2Q8
27 2Q9
SH00081
FUNCTION TABLE
INPUTS
OUTPUTS
nOE nLE nDx nQ0 – nQ9
OPERATING MODE
LH
L
LH H
L
H
Transparent
L
L
l
h
L
H
Latched
HX
X
Z
High impedance
LL
X
NC
Hold
H=
h=
L=
l=
=
NC=
X=
Z=
HIGH voltage level
HIGH voltage level one set-up time prior to the HIGH-to-LOW
LE transition
LOW voltage level
LOW voltage level one set-up time prior to the HIGH-to-LOW
LE transition
HIGH-to-LOW LE transition
No change
Don’t care
High impedance “off” state
3



74ABT16841A datasheets pdf
Total : 11 Pages
Download Full Datasheet File