74148 Datasheet and Specifications PDF

This priority encoder utilizes advanced silicon-gate CMOS technology It has the high noise immunity and low power consumption typical of CMOS circuits as well as the speeds and output drive similar to.

Y Typical propagation delay 13 ns Y Wide supply voltage range 2V
* 6V Connection Diagram Dual-In-Line Package Truth Table Order Number MM54HC148 or MM74HC148 TL F 9390
* 1 Inputs Outputs EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO HXXXXXXXX H H H H H L HHHHHHHH H H H H L L XXXXXXXL L L L L H L XXXXXX.

10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54 / 74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest .

fferences between the LS148 and the LS748 are that (1) Pin 10 (input 0) has a fan-in of 2 on the LS748 versus a fan-in of 1 on the LS148; (2) Pins 1, 2, 3, 4, 11, 12 and 13 (inputs 1, 2, 3, 4, 5, 6, 7) have a fan-in of 3 on the LS748 versus a fan-in of 2 on the LS148. The only ac difference is that .

ordering information These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. The ’147 and ’LS147 devices encode nine data lines to four-l.

priority decoding of the inputs to ensure that only the highest-order data line is encoded. The ’147 and ’LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic l.