| Part Number | 74F821 Datasheet |
|---|---|
| Manufacturer | National Semiconductor |
| Overview | The ’F821 is a 10-bit D-type flip-flop with TRI-STATE true outputs arranged in a broadside pinout The ’F821 is functionally and pin compatible with the AMD’s Am29821 Features Y Y TRI-STATE Outputs D. Y Y TRI-STATE Outputs Direct replacement for AMD’s Am29821 Commercial 74F821SPC Military Package Number N24C Package Description 24-Lead (0 300 Wide) Molded Dual-In-Line 24-Lead (0 300 Wide) Ceramic Dual-In-Line 24-Lead (0 300 Wide) Molded Small Outline JEDEC 24-Lead Cerpack 24-Lead Ceramic Lea. |
74F821 Datasheet and Specifications PDF
The 74F821 is a 10-Bit D-Type Flip-Flop.
Key Specifications
| Package | DIP |
|---|---|
| Mount Type | Through Hole |
| Pins | 24 |
| Operating Voltage | 5 V |
| Max Voltage (typical range) | 5.5 V |
| Min Voltage (typical range) | 4.5 V |
| Logic Function | D-Type, Flip-Flop |
| Clock Edge Trigger | Positive Edge |
| Part Number | 74F821 Datasheet |
|---|---|
| Description | 10-Bit D-Type Flip-Flop |
| Manufacturer | Fairchild Semiconductor |
| Overview | The 74F821 is a 10-bit D-type flip-flop with 3-STATE true outputs arranged in a broadside pinout. Features s 3-STATE Outputs Ordering Code: Order Number 74F821SC 74F821SPC Package Number M24B N24C P. s 3-STATE Outputs Ordering Code: Order Number 74F821SC 74F821SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Spe. |
| Part Number | 74F821 Datasheet |
|---|---|
| Description | Bus interface registers |
| Manufacturer | Philips Semiconductors |
| Overview |
The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carryin.
flip-flops
* High speed parallel registers with positive edge-triggered D-type * High performance bus interface buffering for wide data/address paths or busses carrying parity * High impedance PNP base inputs for reduced loading (20µA in high and low states) * IIL is 20µA vs 1000µA for AM29821 se. |