| Part Number | 74F825 Datasheet |
|---|---|
| Manufacturer | Fairchild Semiconductor |
| Overview | The 74F825 is an 8-bit buffered register. It has Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems. Also included in the 74F825 ar. which are ideal for parity bus interfacing in high performance microprogramming systems. Also included in the 74F825 are multiple enables that allow multi-user control of the interface. Features s 3-STATE output s Clock enable and clear s Multiple output enables Ordering Code: Order Number 74F825S. |
74F825 Datasheet and Specifications PDF
The 74F825 is a 8-Bit D-Type Flip-Flop.
Key Specifications
| Package | SOP |
|---|---|
| Mount Type | Surface Mount |
| Pins | 24 |
| Operating Voltage | 5 V |
| Max Voltage (typical range) | 5.5 V |
| Min Voltage (typical range) | 4.5 V |
| Logic Function | D-Type, Flip-Flop |
| Clock Edge Trigger | Positive Edge |
| Part Number | 74F825 Datasheet |
|---|---|
| Description | 8-Bit D-Type Flip-Flop |
| Manufacturer | National Semiconductor |
| Overview | The ’F825 is an 8-bit buffered register It has Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems Also included in the ’F825 are mu. which are ideal for parity bus interfacing in high performance microprogramming systems Also included in the ’F825 are multiple enables that allow multiuser control of the interface The ’F825 is functionally and pin compatible with AMD’s Am29825 Features Y Y Y Y TRI-STATE output Clock enable and c. |
| Part Number | 74F825 Datasheet |
|---|---|
| Description | Bus interface registers |
| Manufacturer | Philips Semiconductors |
| Overview |
The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carryin.
flip-flops
* High speed parallel registers with positive edge-triggered D-type * High performance bus interface buffering for wide data/address paths or busses carrying parity * High impedance PNP base inputs for reduced loading (20µA in high and low states) * IIL is 20µA vs 1000µA for AM29821 se. |