| Part Number | 74HCT595 Datasheet |
|---|---|
| Manufacturer | Diodes Incorporated |
| Overview |
Pin Assignments
The 74HCT595 is an high speed CMOS device that is designed to be pin compatable with 74LS low power Schottky types.
An eight bit shift register accpets data from the serial input (D.
* Supply Voltage Range from 4.5V to 5.5V * Sinks or sources 8mA at VCC = 4.5V * CMOS low power consumption * Schmitt Trigger Action at All Inputs * Inputs accept up to 6.0V * ESD Protection Tested per JESD 22 Exceeds 200-V Machine Model (A115-A) Exceeds 2000-V Human Body Model (A114-A) Exceeds 1000-. |
74HCT595 Datasheet and Specifications PDF
The 74HCT595 is a 8-BIT SHIFT REGISTER.
Key Specifications
| Package | SOP |
|---|---|
| Mount Type | Surface Mount |
| Pins | 16 |
| Operating Voltage | 5 V |
| Max Voltage (typical range) | 5.5 V |
| Min Voltage (typical range) | 4.5 V |
| Logic Function | Shift Register |
| Clock Edge Trigger | Positive Edge |
| Part Number | 74HCT595 Datasheet |
|---|---|
| Description | 8-bit serial-in serial or parallel-out shift register |
| Manufacturer | NXP Semiconductors |
| Overview | The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device feat. a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH tr. |
| Part Number | 74HCT595 Datasheet |
|---|---|
| Description | serial or parallel-out shift register |
| Manufacturer | Nexperia |
| Overview | The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device feat. a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH tr. |