| Part Number | 74VHC02 |
|---|---|
| Manufacturer | Fairchild Semiconductor |
| Overview |
The VHC02 is an advanced high-speed CMOS 2-Input NOR Gate fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintainin.
* High Speed: tPD = 3.6ns (Typ.) at VCC = 5V * Low power dissipation: ICC = 2µA (Max.) at TA = 25°C * High noise immunity: VNIH = VNIL = 28% VCC (Min.) * Power down protection is provided on all inputs * Low noise: VOLP = 0.8V (Max.) * Pin and function compatible with 74HC02 General Description The. |
74VHC02 Datasheet
The 74VHC02 is a Quad 2-Input NOR Gate.
| Part Number | 74VHC02 |
|---|---|
| Description | QUAD 2-INPUT NOR GATE |
| Manufacturer | STMicroelectronics |
| Overview | The 74VHC02 is an advanced high-speed CMOS QUAD 2-INPUT NOR GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The internal circuit is composed of 3 stages in. ace 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Figure 1: Pin Connection And IEC Logic Symbols November 2004 Rev. 5 1/11 74VHC02 Figure 2: Input Equivalent Circuit Table 2: Pin Desc. |
| Part Number | 74VHC02 |
|---|---|
| Description | Quad 2-Input NOR Gate |
| Manufacturer | onsemi |
| Overview |
The VHC02 is an advanced high-speed CMOS 2-Input NOR Gate fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintainin.
* High Speed: tPD = 3.6ns (Typ.) at VCC = 5V * Low power dissipation: ICC = 2µA (Max.) at TA = 25°C * High noise immunity: VNIH = VNIL = 28% VCC (Min.) * Power down protection is provided on all inputs * Low noise: VOLP = 0.8V (Max.) * Pin and function compatible with 74HC02 General Description The. |
| Part Number | 74VHC02 |
|---|---|
| Description | Quad 2-input NOR gate |
| Manufacturer | Nexperia |
| Overview |
The 74VHC02; 74VHCT02 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7-A. The 74VHC02; 74VHCT0.
and benefits
* Balanced propagation delays * All inputs have a Schmitt-trigger action * Inputs accept voltages higher than VCC * Input levels: * The 74VHC02 operates with CMOS input level * The 74VHCT02 operates with TTL input level * ESD protection: * HBM JESD22-A114E exceeds 2000 V * MM JESD22-A11. |