| Part Number | CY2SSTV850 |
|---|---|
| Manufacturer | Cypress |
| Overview |
This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and differential data input and output levels. This device is a zero-delay buffer that distributes a differential clock input pair .
* Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications * 1:10 differential outputs * External Feedback pins (FBINT, FBINC) are used to synchronize the outputs to the clock input * SSCG: Spread Aware™ for EMI reduction * 48-pin SSOP and TSSOP packages * Conforms to . |
CY2SSTV850 Datasheet
The CY2SSTV850 is a Differential Clock Buffer/Driver.
| Part Number | CY2SSTV850 |
|---|---|
| Description | Differential Clock Buffer/Driver |
| Manufacturer | Silicon Labs |
| Overview |
This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and differential data input and output levels.
This device is a zero-delay buffer that distributes a differential clock input pair .
* Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications * 1:10 differential outputs * External Feedback pins (FBINT, FBINC) are used to synchronize the outputs to the clock input * SSCG: Spread Aware™ for EMI reduction * 48-pin SSOP and TSSOP packages * Conforms to . |