The MC100LVEL39 is a Clock Generation Chip.
| Package | SOP |
|---|---|
| Mount Type | Surface Mount |
| Pins | 20 |
| Operating Voltage | 3.3 V |
| Max Voltage (typical range) | 3.8 V |
| Min Voltage (typical range) | 3 V |
| Logic Function | Clock |
| Max Frequency | 1 GHz |
| Part Number | MC100LVEL39 Datasheet |
|---|---|
| Manufacturer | onsemi |
| Overview |
The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip
designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the commo.
SOIC *20 WB DW SUFFIX CASE 751D MARKING DIAGRAM* 20 100LVEL39 AWLYYWWG 1 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. * 50 ps Maximum Output-to-Output Skew * Synchronous En. |
| Part Number | MC100LVEL39 Datasheet |
|---|---|
| Description | 2/4 /4/6 Clock Generation Chip |
| Manufacturer | Motorola Semiconductor |
| Overview | PIN CLK EN MR VBB Q0, Q1 Q2, Q3 DIVSEL FUNCTION Diff Clock Inputs Sync Enable Master Reset Reference Output Diff ÷2/4 Outputs Diff ÷4/6 Outputs Frequency Select Input FUNCTION TABLE CLK Z ZZ X EN L H. single-ended input conditions, as a result, this pin can only source/sink up to 0.5mA of current. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock p. |
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