Si512 Datasheet and Specifications PDF

16 6.1 ISO/IEC 14443 A functionality .

and benefits 8 3 Quick reference data 10 4 Block diagram.

 Broadcast video  Switches/routers  Telecom  FPGA/ASIC clock generation The Si512/513 dual frequency XO utilizes Silicon Laboratories' advanced PLL technology to provide any frequency from 100 k.

* Supports any frequency from
* 3.3, 2.5, or 1.8 V operation 100 kHz to 250 MHz
* Differential (LVPECL, LVDS,
* Two selectable output frequencies HCSL) or CMOS output options
* Low-jitter operation
* Optional integrated 1:2 CMOS
* 2 to 4 week lead times fanout buffer
* Total stability incl.