SN54LS174 Datasheet
SN54LS174 Datasheet (Motorola Semiconductor)
Motorola Semiconductor
The LS174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input’s state is transferred to .
6
HIGH D0
* D5 CP MR Q0
* Q5 Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Outputs (Note b) 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L.
LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L.
1
D SUFFIX SOIC CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Cer.
SN54LS174 Datasheet (Texas Instruments)
Texas Instruments
SN54174, SN54175, SN54LS174, SN54LS175, SN54S174, SN54S175, SN74174, SN74175, SN74LS174, SN74LS175, SN74S174, SN74S175 HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR SDLS068A – DECEMBER 1972 – REVISED OCT.
2001
*POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3
SN54174, SN54175, SN74174, SN74175 HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDLS068A
* DECEMBER 1972
* REVISED OCTOBER 2001
*4 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SN54LS174, SN54LS175, SN74LS174, SN74LS175 HEX/QUADRUPLE D-TYPE FLIP-FLOP.