UF3C120080K3S Datasheet and Specifications PDF

This SiC FET device is based on a unique ‘cascode’ circuit configuration, in which a normally-on SiC JFET is co-packaged with a Si MOSFET to produce a normally-off SiC FET device. The device’s standar.

* Typical On-resistance RDS(on),typ of 80 mW
* Maximum Operating Temperature of 175 C
* Excellent Reverse Recovery
* Low Gate Charge
* Low Intrinsic Capacitance
* ESD Protected, HBM Class 2
* Very Low Switching Losses (required RC-snubber loss negligible under typical operating conditions)
* This D.

This SiC FET device is based on a unique ‘cascode’ circuit configuration, in which a normally-on SiC JFET is co-packaged with a Si MOSFET to produce a normally-off SiC FET device. The device’s standa.

w Typical on-resistance RDS(on),typ of 80mW w Maximum operating temperature of 175°C w Excellent reverse recovery w Low gate charge w Low intrinsic capacitance w ESD protected, HBM class 2 w Very low switching losses (required RC-snubber loss negligible under typical operating conditions) . Typic.