144-Bit Datasheet | Specifications & PDF Download

CY7C1618KV18/CY7C1620KV18 144-Mbit DDR II SRAM Two-Word Burst Architecture 144-Mbit DDR II SRAM Two-Word Burst Architecture Features ■ 144-Mbit densi

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CY7C1613KV18/CY7C1615KV18 144-Mbit QDR® II SRAM Four-Word Burst Architecture 144-Mbit QDR® II SRAM Four-Word Burst Architecture Features ■ Separate i

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CY7C4121KV13/CY7C4141KV13 144-Mbit QDR™-IV HP SRAM 144-Mbit QDR™-IV HP SRAM Features ■ 144-Mbit density (8M ×18, 4M ×36) ■ Total Random Transaction R

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CY7C1643KV18/CY7C1645KV18 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 144-Mbit QDR® II+ SRAM Four-Word Burst Archite

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Ordering number : EN*5088C CMOS IC LC372100PP, PM, PT-10/20LV 2 MEG (262144 words × 8 bits) Mask ROM Internal Clocked Silicon Gate Preliminary Overv

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CY7C1625KV18 CY7C1612KV18 CY7C1614KV18 144-Mbit QDR® II SRAM Two-Word Burst Architecture 144-Mbit QDR® II SRAM Two-Word Burst Architecture Features ■

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LTC1448 Dual 12-Bit Rail-to-Rail Micropower DAC FEATURES s s s s s s s DESCRIPTION The LTC®1448 is a dual rail-to-rail voltage output, 12-bit digital

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CY7C1618KV18/CY7C1620KV18 144-Mbit DDR II SRAM Two-Word Burst Architecture 144-Mbit DDR II SRAM Two-Word Burst Architecture Features ■ 144-Mbit densi

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LPC185x/3x/2x/1x 32-bit ARM Cortex-M3 MCU; up to 1 MB flash and 136 kB SRAM; Ethernet, two High-speed USB, LCD, EMC Rev. 5.3 — 10 January 2020 Prod

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LPC1850/30/20/10 32-bit ARM Cortex-M3 flashless MCU; up to 200 kB SRAM; Ethernet, two HS USB, LCD, and external memory controller Rev. 6.8 — 10 Janu

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LPC1850/30/20/10 32-bit ARM Cortex-M3 flashless MCU; up to 200 kB SRAM; Ethernet, two HS USB, LCD, and external memory controller Rev. 6.8 — 10 Janu

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LPC1850/30/20/10 32-bit ARM Cortex-M3 flashless MCU; up to 200 kB SRAM; Ethernet, two HS USB, LCD, and external memory controller Rev. 6.8 — 10 Janu

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LPC43S5x/S3x 32-bit ARM Cortex-M4/M0 MCU; up to 1 MB flash and 136 kB SRAM; Ethernet, 2 x USB, LCD, EMC, AES engine Rev. 1.3 — 13 January 2020 Prod

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Ordering number : EN*5088C CMOS IC LC372100PP, PM, PT-10/20LV 2 MEG (262144 words × 8 bits) Mask ROM Internal Clocked Silicon Gate Preliminary Overv

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CY7C1613KV18/CY7C1615KV18 144-Mbit QDR® II SRAM Four-Word Burst Architecture 144-Mbit QDR® II SRAM Four-Word Burst Architecture Features ■ Separate i

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LPC185x/3x/2x/1x 32-bit ARM Cortex-M3 MCU; up to 1 MB flash and 136 kB SRAM; Ethernet, two High-speed USB, LCD, EMC Rev. 5.3 — 10 January 2020 Prod

(17 views)

LPC185x/3x/2x/1x 32-bit ARM Cortex-M3 MCU; up to 1 MB flash and 136 kB SRAM; Ethernet, two High-speed USB, LCD, EMC Rev. 5.3 — 10 January 2020 Prod

(17 views)