M5M5V5636UG-16 Datasheet, Features, Application

M5M5V5636UG-16 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

DESCRIPTION The M5M5V5636UG is a family of 18M bit.

Renesas

M5M5V5636UG-16 - 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

DESCRIPTION The M5M5V5636UG is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit. It is designed to eliminate dead bus cycles .

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