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Analog Devices Semiconductor Electronic Components Datasheet

AD9992 Datasheet

12-Bit CCD Signal Processor

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AD9992 pdf
12-Bit CCD Signal Processor with
Precision Timing Generator
AD9992
FEATURES
1.8 V AFETG core
Internal LDO regulator and charge pump circuitry
Compatibility with 3 V or 1.8 V systems
24 programmable vertical clock outputs
Correlated double sampler (CDS) with −3 dB, 0 dB,
+3 dB, and +6 dB gain
6 dB to 42 dB, 10-bit variable gain amplifier (VGA)
12-bit, 40 MHz ADC
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with 400 ps resolution
On-chip 3 V horizontal and RG drivers
General-purpose outputs (GPOs) for shutter and
system support
On-chip driver for external crystal
On-chip sync generator with external sync input
105-lead CSP_BGA package, 8 mm × 8 mm, 0.65 mm pitch
APPLICATIONS
Digital still cameras
GENERAL DESCRIPTION
The AD9992 is a highly integrated CCD signal processor for
digital still camera applications. It includes a complete analog
front end with analog to digital conversion combined with
a full-function programmable timing generator. The timing
generator is capable of supporting up to 24 vertical clock signals
to control advanced CCDs. A Precision Timing™ core allows
adjustment of high speed clocks with approximately 400 ps
resolution at 40 MHz operation. The AD9992 also contains
eight general-purpose inputs/outputs that can be used for
shutter and system functions.
The AD9992 is specified at pixel rates of up to 40 MHz. The
analog front end includes black level clamping, CDS, VGA, and
a 12-bit analog-to-digital converter (ADC). The timing generator
provides all the necessary CCD clocks: RG, H-clocks, V-clocks,
sensor gate pulses, substrate clock, and substrate bias control.
Operation is programmed using a 3-wire serial interface.
The AD9992 is specified over an operating temperature range
of −25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
CCDIN
CDS
6dB TO 42dB
VGA
VREF
12-BIT
ADC
AD9992
12
DOUT
–3dB, 0dB, +3dB, +6dB
3V INPUT
1.8V OUTPUT
LDO
REG
1.8V INPUT
3V OUTPUT
CHARGE
PUMP
RG
HL HORIZONTAL
8 DRIVERS
H1 TO H8
XV1 TO XV24
XSUBCK
24
VERTICAL
TIMING
CONTROL
8
CLAMP
INTERNAL CLOCKS
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
INTERNAL
REGISTERS
SL
SCK
SDATA
GPO1 TO GPO8
HD VD SYNC CLI CLO
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2007 Analog Devices, Inc. All rights reserved.


Analog Devices Semiconductor Electronic Components Datasheet

AD9992 Datasheet

12-Bit CCD Signal Processor

No Preview Available !

AD9992 pdf
AD9992
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Digital Specifications ................................................................... 4
Analog Specifications................................................................... 5
Timing Specifications .................................................................. 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 11
Equivalent Circuits ......................................................................... 12
Terminology .................................................................................... 13
System Overview ............................................................................ 14
High Speed Precision Timing Core........................................... 15
Horizontal Clamping and Blanking......................................... 19
Horizontal Timing Sequence Example.................................... 25
Vertical Timing Generation ...................................................... 26
Vertical Sequences (VSEQ) ....................................................... 29
Vertical Timing Example........................................................... 45
REVISION HISTORY
10/07—Rev. B to Rev. C
Changes to Vertical Timing Generation Section........................ 26
Changes to Vertical Sequences (VSEQ) Section......................... 29
Changes to Vertical Timing Example Section ............................ 45
Changes to Power-Up Sequence for Master Mode Section ...... 64
Changes to Figure 80...................................................................... 70
Changes to Figure 81...................................................................... 71
9/07—Rev. A to Rev. B
Added Figure 2.................................................................................. 4
Deleted Endnote in Table 3 ............................................................. 5
Added Address 0x17 Bit 17 Information to Table 30................. 75
Shutter Timing Control ............................................................. 47
Substrate Clock Operation (SUBCK) ...................................... 47
Field Counters............................................................................. 50
General-Purpose Outputs (GPOs) .......................................... 51
GP Look-Up Tables (LUT)........................................................ 55
Complete Exposure/Readout Operation Using Primary
Counter and GPO Signals ......................................................... 56
Manual Shutter Operation Using Enhanced SYNC Modes.. 58
Analog Front End Description and Operation ...................... 62
Power-Up Sequence for Master Mode..................................... 64
Standby Mode Operation .......................................................... 67
CLI Frequency Change.............................................................. 67
Circuit Layout Information........................................................... 69
Typical 3 V System ..................................................................... 69
Typical 1.8 V System .................................................................. 69
External Crystal Application .................................................... 69
Serial Interface Timing .............................................................. 72
Layout of Internal Registers ...................................................... 73
Updating New Register Values ................................................. 74
Complete Register Listing ............................................................. 75
Outline Dimensions ....................................................................... 92
Ordering Guide .......................................................................... 92
7/07—Rev. 0 to Rev. A
Changes to Table 3 and Related Endnote.......................................5
Added Slave Mode and SHP/SHD Information to Table 4..........6
Changes to Table 5.............................................................................7
Changes to Table 7.............................................................................8
Changes to Figure 18...................................................................... 17
Changes to Figure 75...................................................................... 66
Changes to Figure 81...................................................................... 71
1/06—Revision 0: Initial Version
Rev. C | Page 2 of 92


Part Number AD9992
Description 12-Bit CCD Signal Processor
Maker Analog Devices
Total Page 30 Pages
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