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Austin Semiconductor
Austin Semiconductor

AS5SP128K32DQ Datasheet Preview

AS5SP128K32DQ Datasheet

Plastic Encapsulated Microcircuit 4.0Mb

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AS5SP128K32DQ pdf
Austin Semiconductor, Inc.
COTS PEM
AS5SP128K32DQ
SSRAM
Plastic Encapsulated Microcircuit
4.0Mb, 128K x 32, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
Features
Synchronous Operation in relation to the input Clock
2 Stage Registers resulting in Pipeline operation
On chip address counter (base +3) for Burst operations
Self-Timed Write Cycles
On-Chip Address and Control Registers
Byte Write support
Global Write support
On-Chip low power mode [powerdown] via ZZ pin
Interleaved or Linear Burst support via Mode pin
Three Chip Enables for ease of depth expansion without Data
Contention.
Two Cycle load, Single Cycle Deselect
Asynchronous Output Enable (OE\)
Three Pin Burst Control (ADSP\, ADSC\, ADV\)
3.3V Core Power Supply
3.3V/2.5V IO Power Supply
JEDEC Standard 100 pin TQFP Package, MS026-D/BHA
Available in Industrial, Enhanced, and Mil-Temperature
Operating Ranges
NC
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSRAM [SPB]
80 NC
79 DQb
78 DQb
77 VDDQ
76 VSSQ
75 DQb
74 DQb
73 DQb
72 DQb
71 VSSQ
70 VDDQ
69 DQb
68 DQb
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSSQ
59 DQa
58 DQa
57 DQa
56 DQa
55 VSSQ
54 VDDQ
53 DQa
52 DQa
51 NC
Fast Access Times
Parameter
Cycle Time
Clock Access Time
Output Enable Access Time
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Block Diagram
Symbol
tCYC
tCD
tOE
200Mhz
5.0
3.0
3.0
166Mhz
6.0
3.5
3.5
133Mhz
7.5
4.0
4.0
100Mhz
10.0
5.0
5.0
Units
ns
ns
ns
General Description
ASI’s AS5SP128K32DQ is a 4.0Mb High Performance
Synchronous Pipeline Burst SRAM, available in multiple
OE\ temperature screening levels, fabricated using High Performance
ZZ CMOS technology and is organized as a 128K x 32. It integrates
CLK address and control registers, a two (2) bit burst address counter
CE1\
CE2
CE3\
BWE\
BWx\
GW\
ADV
ADSC\
ADSP\
MODE
A0-Ax
CONTROL
BLOCK
BURST CNTL.
Address
Registers
Row
Decode
Column
Decode
I/O Gating and Control
Memory Array
x36
SBP
T Synchronous Pipeline
Burst
N Two (2) cycle load
N One (1) cycle
de-select
N One (1) cycle latency
on Mode change
supporting four (4) double-word transfers. Writes are internally
self-timed and synchronous to the rising edge of clock.
Output Output
Register Driver
Input
Register
DQx, DQPx
ASI’s AS5SP128K32DQ includes advanced control options
including Global Write, Byte Write as well as an Asynchronous
Output enable. Burst Cycle controls are handled by three (3)
input pins, ADV, ADSP\ and ADSC\. Burst operation can be
initiated with either the Address Status Processor (ADSP\) or
Address Status Cache controller (ADSC\) inputs. Subsequent
burst addresses are generated internally in the system’s burst
sequence control block and are controlled by Address Advance
(ADV) control input.
AS5SP128K32DQ
Revision 1.1 07/29/04
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
1



Austin Semiconductor
Austin Semiconductor

AS5SP128K32DQ Datasheet Preview

AS5SP128K32DQ Datasheet

Plastic Encapsulated Microcircuit 4.0Mb

No Preview Available !

AS5SP128K32DQ pdf
Austin Semiconductor, Inc.
COTS PEM
AS5SP128K32DQ
SSRAM
Pin Description/Assignment Table
Signal Name
Clock
Symbol
CLK
Address
A0, A1
Address
A
Chip Enable
Chip Enable
Global Write Enable
Byte Enables
Byte Write Enable
Output Enable
Address Strobe Controller
CE1\, CE3\
CE2
GW\
BWa\, BWb\,
BWc\, BWd\
BWE\
OE\
ADSC\
Address Strobe from Processor ADSP\
Address Advance
Power-Down
ADV
ZZ
Type
Input
Input
Input(s)
Input
Input
Input
Input
Pin
89
37, 36
35, 34, 33, 32, 100,
99, 82, 81, 44, 45, 46,
47, 48, 49, 50
98, 92
97
88
93, 94, 95, 96
Description
This input registers the address, data, enables, Global and Byte
writes as well as the burst control functions
Low order, Synchronous Address Inputs and Burst counter
address inputs
Synchronous Address Inputs
Active Low True Chip Enables
Active High True Chip Enable
Active Low True Global Write enable. Write to all bits
Active Low True Byte Write enables. Write to byte segments
Input
Input
Input
Input
Input
Input
87 Active Low True Byte Write Function enable
86 Active Low True Asynchronous Output enable
85 Address Strobe from Controller. When asserted LOW, Address is
captured in the address registers and A0-A1 are loaded into the Burst
When ADSP\ and ADSC are both asserted, only ADSP is recognized
84 Synchronous Address Strobe from Processor. When asserted LOW,
Address is captured in the Address registers, A0-A1 is registered in
the burst counter. When both ADSP\ and ADSC\ or both asserted,
only ADSP\ is recognized. ADSP\ is ignored when CE1\ is HIGH
83 Advance input Address. When asserted HIGH, address in burst
counter is incremented.
64 Asynchronous, non-time critical Power-down Input control. Places
the chip into an ultra low power mode, with data preserved.
Data Input/Outputs
Burst Mode
Power Supply [Core]
Ground [Core]
Power Supply I/O
I/O Ground
No Connection(s)
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Logic Block Diagram
A0, A1, Ax
MODE
ADV\
CLK
ADSC\
ADSP\
BWd\
BWc\
BWb\
BWa\
BWE\
GW\
CE1\
CE2
CE3\
OE\
DQa, DQb, DQc Input/
DQd
Output
MODE
VDD
VSS
VDDQ
VSSQ
NC
Input
Supply
Supply
Supply
Supply
NA
52, 53, 56, 57, 58, 59,
62, 63, 68, 69, 72, 73,
74, 75, 78, 79, 2, 3, 6,
7, 8, 9, 12, 13, 18, 19,
22, 23, 24, 25, 28, 29
31
91, 15, 41, 65
90, 17, 40, 67
4, 11, 20, 27, 54, 61,
70, 77
5, 10, 21, 26, 55, 60,
71, 76
14, 16, 38, 39, 66
38,39,42,43
Bidirectional I/O Data lines. As inputs they reach the memory
array via an input register, the address stored in the register on the
rising edge of clock. As and output, the line delivers the valid data
stored in the array via an output register and output driver. The data
delieverd is from the previous clock period of the READ cycle.
Interleaved or Linear Burst mode control
Core Power Supply
Core Power Supply Ground
Isolated Input/Output Buffer Supply
Isolated Input/Output Buffer Ground
No connections to internal silicon
ADDRESS
REGISTER
2 A0, A1
Burst
CounterQ1
CLRLaongdic Q0
Byte Write
Register
DQd, DQPd
Byte Write
Register
DQc, DQPc
Byte Write
Register
DQb, DQPb
Byte Write
Register
DQa, DQPa
Enable
Register
Pipeline
Enable
Byte Write
Driver
DQd, DQPd
Byte Write
Driver
DQc, DQPc
Byte Write
Driver
DQb, DQPb
Byte Write
Driver
DQa, DQPa
Memory
Array
Sense
Amps
Output
Registers
Output
Buffers
Input
Registers
DQx,
DQPx
ZZ
AS5SP128K32DQ
Revision 1.1 07/29/04
Sleep
Control
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
2


Part Number AS5SP128K32DQ
Description Plastic Encapsulated Microcircuit 4.0Mb
Maker Austin Semiconductor
Total Page 10 Pages
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