Austin Semiconductor, Inc.
Ultra Low Power
128K x 8 SRAM
WITH DUAL CHIP ENABLE
ULTRA LOW POWER
AVAILABLE AS MILITARY
•MIL-STD-883, para. 1.2.2 compliant
• High Speed: 30 ns
• Low active power: 715 mW worst case
• Low CMOS standby power: 3.3 mW worst case
• 2.0V data retention, Ultra Low 0.3mW worst
case power dissipation
• Battery backup applications
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1\, CE2, and OE\ options
Ceramic DIP (400 mil)
C No. 111
Military (-55°C to +125°C)
2V data retention/very low power LL
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32-Pin DIP (C)
The MT5C1008 SRAM is a high-performance CMOS
static RAM organized as 131, 072 words by 8 bits, offering low
active power and ultra low standby and data retention current
levels. Easy memory expansion is provided by an active LOW
Chip Enable (CE1\), an active HIGH Chip Enable (CE2), and
active Low Output Enable (OE\), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable
One (CE1\) and Write Enable (WE\) inputs LOW and Chip
Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A16).
Reading from the device is accomplished by taking
Chip Enable One (CE1\) and Output Enable (OE\) LOW while
forcing Write Enable (WE\) and Chip Enable Two (CE2) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output (I/O0 through I/O7) are placed
in a high-impedance state when the device is deselected (CE1\)
HIGH or CE2 LOW), the outputs are disabled (OE\ HIGH), or
during a write operation (CE1\ LOW, CE2 HIGH, and WE\ LOW).
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.