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Cypress Semiconductor Electronic Components Datasheet

CYU01M16ZCC Datasheet

16-Mbit (1M x 16) Pseudo Static RAM

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CYU01M16ZCC pdf
PRELIMINARY
CYU01M16ZCC
MoBL3™
16-Mbit (1M x 16) Pseudo Static RAM
Features
• Wide voltage range: 2.2V–3.6V
• Access Time: 70 ns
• Ultra-low active power
— Typical active current: 3 mA @ f = 1 MHz
— Typical active current: 18 mA @ f = fmax
• Ultra low standby power
• 16-word Page Mode
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Deep Sleep Mode
• Offered in a Lead-Free 48-ball BGA Package
• Operating Temperature: –40°C to +85°C
Functional Description[1]
The CYU01M16ZCC is a high-performance CMOS Pseudo
Static RAM organized as 1M words by 16 bits that supports an
asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
can be put into standby mode when deselected (CE HIGH or
both BHE and BLE are HIGH). The input/output pins (I/O0
through I/O15) are placed in a high-impedance state when:
deselected (CE HIGH), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW and WE
LOW).
Writing to the device is accomplished by taking Chip Enable
(CE LOW) and Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0 through
I/O7), is written into the location specified on the address pins
(A0 through A19). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A19).
Reading from the device is accomplished by taking Chip
Enables (CE LOW) and Output Enable (OE) LOW while
forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE)
is LOW, then data from the memory location specified by the
address pins will appear on I/O0 to I/O7. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O8 to
I/O15. Refer to the truth table for a complete description of read
and write modes.
Deep Sleep Mode is enabled by driving ZZ LOW. See the Truth
Table for a complete description of Read, Write, and Deep
Sleep mode.
Logic Block Diagram
DATA IN DRIVERS
A
A
8
9
A10
A11
A12
A13
1M × 16
RAM Array
A14
AA1156
AAA111987
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
Power-Down
Circuit
BHE
BLE
BHE
WE
OE
BLE
CE
CE ZZ
Refresh/Power-down
Circuit
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
www.DDaotacSuhmeeetn4Ut #.n:e3t 8-05602 Rev. *F
Revised January 16, 2006


Cypress Semiconductor Electronic Components Datasheet

CYU01M16ZCC Datasheet

16-Mbit (1M x 16) Pseudo Static RAM

No Preview Available !

CYU01M16ZCC pdf
PRELIMINARY
CYU01M16ZCC
MoBL3™
Pin Configuration[2, 3]
48-Ball VFBGA
Top View
12
34
56
BLE OE A0 A1 A2 ZZ
A
I/O8 BHE A3 A4 CE I/O0
I/O9 I/O10 A5 A6 I/O1 I/O2
VSS I/O11 A17 A7 I/O3 VCC
VCC I/O12 NC
A16 I/O4 VSS
I/O14 I/O13 A14 A15 I/O5 I/O6
I/O15 A19 A12 A13 WE I/O7
A18 A8 A9 A10 A11
NC
B
C
D
E
F
G
H
Product Portfolio[4]
Product
CYU01M16ZCC
VCC Range (V)
Min.
Typ.[4]
Max.
2.2 3.0 3.6
Speed
(ns)
70
Power Dissipation
Operating ICC (mA)
f = 1MHz
Typ.[4] Max.
f = fmax
Typ.[4] Max.
Standby ISB2 (µA)
Typ.[4] Max.
3 5 18 25 55 70
Low-Power Modes
At power-up, all four sections of the die are activated and the
PSRAM enters into its default state of full memory size and
refresh space. This device provides four different Low-Power
Modes.
1. Reduced Memory Size Operation
2. Partial Array Refresh
3. Deep Sleep Mode
4. Temperature Controlled Refresh
Reduced Memory Size Operation
In this mode, the 16-Mb PSRAM can be operated as a 12-Mbit,
8-Mbit and 4-Mbit memory block. Please refer to “Variable
Address Space Register (VAR)” on page 4 for the protocol to
turn on/off sections of the memory. The device remains in RMS
mode until changes to the Variable Address Space register are
made to revert back to a complete 16-Mbit PSRAM.
Partial Array Refresh
The Partial Array Refresh mode allows customers to turn off
sections of the memory block in the Stand-by mode (with ZZ
tied LOW) to reduce standby current. In this mode the PSRAM
will only refresh certain portions of the memory in the Stand-By
Mode, as configured by the user through the settings in the
Variable Address Register.
Once ZZ returns HIGH in this mode, the PSRAM goes back to
operating in full address refresh. Please refer to “Variable
Address Space Register (VAR)” on page 4 for the protocol to
turn off sections of the memory in Stand-By mode. If the VAR
register is not updated after the power up, the PSRAM will be
in its default state. In the default state the whole memory array
will be refreshed in the Stand-By Mode. The 16-Mbit MoBL3™
is divided into four 4-Mbit sections allowing certain sections to
be active (i.e., refreshed).
Deep Sleep Mode
In this mode, the data integrity in the PSRAM is not
guaranteed. This mode can be used to lower the power
consumption of the PSRAM in an application. This mode can
be enabled and disabled through VAR similar to the RMS and
PAR mode. Deep Sleep Mode is activated by driving ZZ LOW.
The device stays in the deep sleep mode until ZZ is driven
HIGH.
Notes:
2. Ball H6 and E3 can be used to upgrade to a 32M and a 64M density respectively.
3. NC “no connect” - not connected internally to the die.
4.
Typical values are included for reference only and are not guaranteed
and after any design changes that may affect the parameter.
or
tested. Typical
values
are
measured
at VCC = VCC
(typ) and
TA =
25°C.
Tested initially
Document #: 38-05602 Rev. *F
Page 2 of 14


Part Number CYU01M16ZCC
Description 16-Mbit (1M x 16) Pseudo Static RAM
Maker Cypress Semiconductor
Total Page 14 Pages
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