High Voltage Gen.,
Timing and Control
64 x 32
D0014 ILL B01.1
ENDURANCE AND DATA RETENTION
The XL24C02 is designed for applications requiring up to
100,000 write cycles and unlimited read cycles. It pro-
vides 100 years of secure data retention, with or without
power applied, after the execution of 100,000 write
The XL24C02 is ideal for high volume applications requir-
ing low power and low density storage. This device uses
a cost effective, space-saving 8-pin plastic package.
Typical applications include robotics, alarm devices, elec-
tronic locks, meters and instrumentation.
CHARACTERISTICS OF THE I2C BUS
The I2C bus was designed for two-way, two-line serial
communication for different integrated circuits. The two
lines are: a serial data line (SDA), and a serial clock line
(SCL). The SDA line must be connected to a positive
supply by a pull-up resistor, located somewhere on the
bus (See Figure 1). Data transfer between devices may
be initiated with a START condition only when SCL and
SDA are HIGH (bus is not busy).
START and STOP Conditions
When both data and clock lines are HIGH, the bus is
known as “not busy.” A HIGH-to-LOW transition of the
data line, while the clock is HIGH, is defined as the
“START” condition. A LOW-to-HIGH transition of the data
line, while the clock is HIGH, is defined as the “STOP”
condition (See Figure 3).
The XL24C02 is a 2,048-bit serial E2PROM. The device
supports the I2C bidirectional data transmission protocol.
The protocol defines any device that sends data onto the
bus as a “transmitter” and the receiving device as the
“receiver.” The device controlling the data transmission is
the “master,” and the controlled device is the “slave.” In all
cases, the XL24C02 will be a “slave” device, since it never
initiates any data transfers.
Up to eight XL24C02s can be connected to the bus,
selected by the A0, A1 and A2 device addresses. A0, A1
and A2 must be connected to either VCC, VSS or they may
be actively driven. Other devices may be connected to the
bus, but need a different device identification code.
Input Data Protocol
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the clock
HIGH time, because changes on the data line, while SCL
is HIGH will be interpreted as “START” or “STOP” condi-
tion (See Figure 2).