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IA8251 Datasheet Preview

IA8251 Datasheet

Programmable Communication Interface

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IA8251 pdf
IA8251
Page 1 of 4
Advanced Information Sheet
Programmable Communication Interface
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FEATURES
Form, Fit, and Function Compatible with the Intel® 8251A
Packaging options available: 28 Pin Plastic Dip or 28 Pin Plastic Leaded
Chip Carrier
Synchronous and Asynchronous Operation
Full Duplex, Double-Buffered Transmitter and Receiver
Programmable Word Length, Stop Bits, and Parity
Offers Divide-by-1, -16, or –64 Mode
Includes:
- Error Detection
- False Start Detection
- Automatic Break Detection and Handling
- Internal and External Sync Character Detection
The IA8251 uses innovASIC’s innovative new f 3 Program to provide industry with parts that
other vendors have declared obsolete. By specifying parts through this program a customer is
assured of never having a component become obsolete again. This advanced information sheet
assumes the original part has been designed in, and so provides a summary of capabilities only. For
new designs contact innovASIC for more detailed information.
Intel is a registered trademark of Intel Corporation
Package Pinout
D2
D3
RXD
GND
D4
D5
D6
D7
TXC_n
WR_n
CS_n
CD_n
RD_n
RXRDY
(1) IA8251
(2) 28 Pin DIP
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(28)
(27)
(26)
(25)
(24)
(23)
(22)
(21)
(20)
(19)
(18)
(17)
(16)
(15)
D1
D0
VCC
RXC_n
DTR_n
RTS_n
DSR_n
RESET
CLK
TXD
TXEMPTY
CTS_n
SYNDET_BD
TXRDY
D4
D5
D6
D7
TXC_n
WR_n
CS_n
(5)
(6)
(7)
(8)
(9)
(10)
(11)
IA8251
28 Pin LCC
(25) RXC_n
(24) DTR_n
(23) RTS_n
(22) DSR_n
(21) RESET
(20) CLK
(19) TXD
Copyright © 1999, InnovASIC Inc.
Customer Specific IC Solutions



InnovASIC
InnovASIC

IA8251 Datasheet Preview

IA8251 Datasheet

Programmable Communication Interface

No Preview Available !

IA8251 pdf
IA8251
Page 2 of 4
Advanced Information Sheet
Programmable Communication Interface
The IA8251 provides an interface between a microprocessor and a serial communications channel.
The IA8251 receives and transmits data in a variety of configurations including 7- or 8-bit data
words, with odd, even , or no parity, and 1 or 2 stop bits. The transmitter and receiver can be
designed for synchronous or asynchronous operation.
A block diagram is shown in Figure 1.
Functional Block Diagram
Figure 1
INTERNAL DATA
BUS
D7:D0
DATA BUS
BUFFER
GROUP A
PORT A
(8)
TXD
RESET
CLK
CD_n
RD_n
WR_n
CS_n
DSR_n
DTR_n
CTS_n
RTS_n
READ/WRITE
CONTROL
LOGIC
MODEM
CONTROL
GROUP A
PORT C
UPPER (4)
TXRDY
TXEMPTY
TXC_n
GROUP B
PORT C
LOWER
(4)
RXD
GROUP B
PORT B
(8)
RXRDY
RXC_n
SYNDET_BD
Copyright © 1999, InnovASIC Inc.
Customer Specific IC Solutions


Part Number IA8251
Description Programmable Communication Interface
Maker InnovASIC
Total Page 4 Pages
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