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Integrated Device Technology Electronic Components Datasheet

IDT72V3636 Datasheet

(IDT72V36x6) 3.3 VOLT CMOS TRIPLE BUS SyncFIFO

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IDT72V3636 pdf
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3.3 VOLT CMOS TRIPLE BUS
SyncFIFOTM WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2,
1,024 x 36 x 2
IDT72V3626
IDT72V3636
IDT72V3646
.EATURES:
Memory storage capacity:
IDT72V3626–256 x 36 x 2
IDT72V3636–512 x 36 x 2
IDT72V3646–1,024 x 36 x 2
Clock frequencies up to 100 MHz (6.5ns access time)
Two independent FIFOs buffer data between one bidirectional
36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)
18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on
Ports B and C
Select IDT Standard timing (using EFA, EFB, FFA, and FFC flag
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
Serial or parallel programming of partial flags
Big- or Little-Endian format for word and byte bus sizes
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA, CLKB and CLKC may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Pin and functionally compatible versions of 5V operating
IDT723626/723636/723646
Industrial temperature range (–40°C to +85°C) is available
.UNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
MRS1
PRS1
FFA/IRA
AFA
SPM
FS0/SD
FS1/SEN
A0-A35
EFA/ORA
AEA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
36
36
MBF2
Mail 1
Register
36
RAM ARRAY
256 x 36
36
512 x 36
1,024 x 36
FIFO1
Write
Pointer
Read
Pointer
Status Flag
Logic
Programmable Flag
Offset Registers
Timing
Mode
10
FIFO2
Status Flag
Logic
Read
Pointer
Write
Pointer
RAM ARRAY
36 256 x 36
512 x 36
1,024 x 36
36
Mail 2
Register
MBF1
18
B0-B17
Port-B
Control
Logic
CLKB
RENB
CSB
MBB
SIZEB
Common
Port
Control
Logic
(B and C)
EFB/ORB
AEB
BE
FWFT
FFC/IRC
AFC
FIFO2,
Mail2
Reset
Logic
18
Port-C
Control
Logic
MRS2
PRS2
C0-C17
CLKC
WENC
MBC
SIZEC
4665 drw01
IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2001 Integrated Device Technology, Inc. All right reserved. Product specifications subject to change without notice.
AUGUST 2001
DSC-4665/4


Integrated Device Technology Electronic Components Datasheet

IDT72V3636 Datasheet

(IDT72V36x6) 3.3 VOLT CMOS TRIPLE BUS SyncFIFO

No Preview Available !

IDT72V3636 pdf
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
DESCRIPTION:
The IDT72V3626/72V3636/72V3646 are pin and functionally compatible
versiwonwswo.fDthaetaISDhTe7e2t346U2.6c/o7m23636/723646, designed to run off a 3.3V supply
for exceptionally low-power consumption. These devices are a monolithic,
high-speed, low-power, CMOS Triple Bus synchronous (clocked) FIFO
memory which supports clock frequencies up to 100 MHz and has read access
times as fast as 6.5ns. Two independent 256/512/1,024 x 36 dual-port SRAM
FIFOs on board each chip buffer data between a bidirectional 36-bit bus (Port
A) and two unidirectional 18-bit buses (Port B transmits data, Port C receives
data.) FIFO data can be read out of Port B and written into Port C using either
18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations.
These devices are a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
PIN CON.IGURATION
INDEX
W/RA
ENA
CLKA
GND
A35
A34
A33
A32
Vcc
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
BE/FWFT
GND
A22
Vcc
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
Vcc
A12
GND
A11
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
TQFP (PK128-1, order code: PF)
TOP VIEW
2
102 CLKB
101 PRS2
100 VCC
99 C17
98 C16
97 C15
96 C14
95 GND
94 MBC
93 C13
92 C12
91 C11
90 C10
89 C9
88 C8
87 VCC
86 C7
85 C6
84 SIZEB
83 GND
82 C5
81 C4
80 C3
79 C2
78 C1
77 C0
76 GND
75 B17
74 B16
73 SIZEC
72 VCC
71 B15
70 B14
69 B13
68 B12
67 GND
66 B11
65 B10
4665 drw 02


Part Number IDT72V3636
Description (IDT72V36x6) 3.3 VOLT CMOS TRIPLE BUS SyncFIFO
Maker Integrated Device Technology
Total Page 30 Pages
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