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Intersil Electronic Components Datasheet

MD82C237-12 Datasheet

CMOS High Performance Programmable DMA Controller

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MD82C237-12 pdf
82C237
March 1997
CMOS High Performance
Programmable DMA Controller
Features
Description
• Fully Compatible with Intersil 82C37A
- 82C237 May be Used in 8MHz and 12.5MHz 82C37A
Sockets
• Optimized for 10MHz and 12.5MHz 80C286 Systems
• Special Mode Permits 16-Bit, Zero Wait State DMA
Transfers
• High Speed Data Transfers:
- Up to 6.25MBytes/sec with 12.5MHz Clock in
Normal Mode
- Up to 12.5MBytes/sec with 12.5MHz Clock in 16-Bit
Mode
• Compatible with the NMOS 8237A
• Four Independent Maskable Channels with Autoinitial-
ization Capability
• Cascadable to any Number of Channels
• Memory-to-Memory Transfers
• Static CMOS Design Permits Low Power Operation
- ICCSB = 10µA Maximum
- ICCOP = 2mA/MHz Maximum
• Fully TTL/CMOS Compatible
• Internal Registers may be Read from Software
The 82C237 is a modified version of the 82C37A. The
82C237 is fully software and pin for pin compatible with the
82C37A but provides an additional mode for 16-bit DMA
transfers, as well as enhanced speed. Each channel may be
individually programmed for 8-bit or 16-bit data transfers.
The 82C237 controller can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization fea-
ture. DMA requests may be generated by either hardware or
software, and each channel is independently programmable
with a variety of features for flexible operation.
The 82C237 is designed to be used with an external address
latch, such as the 82C82, to demultiplex the most significant
8 bits of address. An additional latch is required to
temporarily store the most significant 8 bits of data if 16-bit
memory-to-memory transfers are desired. The 82C237 can
be used with industry standard microprocessors such as
80C286, 80286, 80C86, 80C88, 8086, 8088, 8085, Z80,
NSC800, 80186 and others. Multimode programmability
allows the user to select from three basic types of DMA
services, and reconfiguration under program control is
possible even with the clock to the controller stopped. Each
channel has a full 64K address and word count range, and
may be programmed to autoinitialize these registers
following DMA termination (end of process).
Ordering Information
PACKAGE
PDIP
PLCC
SBDIP
TEMPERATURE
RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
SMD#
CLCC
SMD#
-55oC to +125oC
8MHz
CP82C237
IP82C237
CS82C237
IS82C237
CD82C237
ID82C237
MD82C237/B
5962-9054304MQA
MR82C237/B
5962-9054304MXA
12.5MHz
CP82C237-12
IP82C237-12
CS82C237-12
IS82C237-12
CD82C237-12
ID82C237-12
MD82C237-12/B
5962-9054305MQA
MR82C237-12/B
5962-9054305MXA
PKG. NO.
E40.6
E40.6
N44.65
N44.65
F40.6
F40.6
F40.6
F40.6
J44.A
J44.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-148
File Number 2965.1


Intersil Electronic Components Datasheet

MD82C237-12 Datasheet

CMOS High Performance Programmable DMA Controller

No Preview Available !

MD82C237-12 pdf
82C237
Pinouts
82C237 (DIP)
TOP VIEW
IOR 1
IOW 2
MEMR 3
MEMW
DWLE
(NOTE)
READY
HLDA
4
5
6
7
ADSTB 8
AEN 9
HRQ 10
CS 11
CLK 12
RESET 13
DACK2 14
DACK3 15
DREQ3 16
DREQ2 17
DREQ1 18
DREQ0 19
(GND) VSS 20
40 A7
39 A6
38 A5
37 A4
36 EOP
35 A3
34 A2
33 A1
32 A0
31 VCC
30 DB0
29 DB1
28 DB2
27 DB3
26 DB4
25 DACK0
24 DACK1
23 DB5
22 DB6
21 DB7
82C237 (CLCC/PLCC)
TOP VIEW
6 5 4 3 2 1 44 43 42 41 40
NC 7
39 A3
NC 8
38 A2
HLDA 9
37 A1
ADSTB 10
36 A0
AEN 11
HRQ 12
35 VCC
34 DB0
CS 13
33 DB1
CLK 14
32 DB2
RESET 15
31 DB3
DACK2 16
NC 17
30 DB4
29 NC
18 19 20 21 22 23 24 25 26 27 28
NOTE: See Pin Description.
Block Diagram
DWLE
EOP
RESET
CS
READY
CLK
AEN
ADSTB
MEMR
MEMW
IOR
IOW
TIMING
AND
CONTROL
DREQ0 -
DREQ3
HLDA
HRQ
DACK0 -
DACK3
4
4
PRIORITY
ENCODER
AND
ROTATING
PRIORITY
LOGIC
DECREMENTOR
TEMP WORD
COUNT REG (16)
INC DECREMENTOR
TEMP ADDRESS
REG (16)
16-BIT BUS
16-BIT BUS
READ BUFFER
READ WRITE BUFFER
BASE
ADDRESS
(16)
BASE
WORD
COUNT
(16)
CURRENT
ADDRESS
(16)
CURRENT
WORD
COUNT
(16)
IO
BUFFER
A0 - A3
OUTPUT
BUFFER
A4 - A7
COMMAND
CONTROL
DATA-WIDTH
(4)
COMMAND
(8)
MASK
(4)
REQUEST
(4)
WRITE
BUFFER
READ
BUFFER
INTERNAL DATA BUS
D0 - D1
IO
BUFFER
MODE
(4 x 6)
STATUS
(8)
TEMPORARY
(8)
4-149


Part Number MD82C237-12
Description CMOS High Performance Programmable DMA Controller
Maker Intersil
Total Page 25 Pages
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