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Motorola Electronic Components Datasheet

F801FA60 Datasheet

DSP56F801FA60

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F801FA60 pdf
Freescale Semiconductor, Inc.
DSP56F801/D
Rev. 13.0, 02/2004
56F801
www.datasheet4u.com
Technical Data
56F801 16-bit Hybrid Controller
• Up to 30 MIPS operation at 60MHz core
frequency
• Up to 40 MIPS operation at 80MHz core
frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
• Hardware DO and REP loops
• 6-channel PWM Module
• Two 4-channel, 12-bit ADCs
• Serial Communications Interface (SCI)
• 8K × 16-bit words Program Flash
• 1K × 16-bit words Program RAM
• 2K × 16-bit words Data Flash
• 1K × 16-bit words Data RAM
• 2K × 16-bit words Boot Flash
• Serial Peripheral Interface (SPI)
• General Purpose Quad Timer
• JTAG/OnCETM port for debugging
• On-chip relaxation oscillator
• 11 shared GPIO
• 48-pin LQFP Package
6
PWM Outputs
Fault Input
A/D1
4 A/D2 ADC
4 VREF
PWMA
RESET
IRQA
6
JTAG/
OnCE
Port
VCAPC VDD
24
VSS
5*
VDDA
VSSA
Digital Reg Analog Reg
Low Voltage
Supervisor
Interrupt
Controller
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
Quad Timer C
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
Quad Timer D
Boot Flash
3
or GPIO
2048 x 16 Flash
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
SCI0
or
2 GPIO
COP/
Watchdog
Application-
SPI Specific
4
or
GPIO
Memory &
Peripherals
••
PAB
PDB
XDB2
CGDB
• • •XAB1
XAB2
INTERRUPT
IPBB
CONTROLS CONTROLS
16 16
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
IPBus Bridge
(IPBB)
16-Bit
56800
Core
PLL
Clock Gen
or Optional
Internal
Relaxation Osc.
*includes TCS pin which is reserved for factory use and is tied to VSS
Figure 1. 56F801 Block Diagram
GPIOB3/XTAL
GPIOB2/EXTAL
© Motorola, Inc., 2004. All rights reserved.
For More Information On This Product,
Go to: www.freescale.com


Motorola Electronic Components Datasheet

F801FA60 Datasheet

DSP56F801FA60

No Preview Available !

F801FA60 pdf
Freescale Semiconductor, Inc.
Part 1 Overview
1.1 56F801 Features
1.1.1www.datasheet4u.com Digital Signal Processing Core
• Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture
• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Two 36-bit accumulators including extension bits
• 16-bit bidirectional barrel shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses and one external address bus
• Four internal data buses and one external data bus
• Instruction set supports both DSP and controller functions
• Controller style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/OnCE debug programming interface
1.1.2 Memory
• Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
• On-chip memory including a low-cost, high-volume Flash solution
— 8K × 16 bit words of Program Flash
— 1K × 16-bit words of Program RAM
— 2K × 16-bit words of Data Flash
— 1K × 16-bit words of Data RAM
— 2K × 16-bit words of Boot Flash
• Programmable Boot Flash supports customized boot code and field upgrades of stored code
through a variety of interfaces (JTAG, SPI)
1.1.3 Peripheral Circuits for 56F801
• Pulse Width Modulator (PWM) with six PWM outputs, two Fault inputs, fault-tolerant design with
deadtime insertion; supports both center- and edge-aligned modes
• Two 12-bit, Analog-to-Digital Converters (ADCs), which support two simultaneous conversions
with two 4-multiplexed inputs; ADC and PWM modules can be synchronized
• General Purpose Quad Timer: Timer D with three pins (or three additional GPIO lines)
• Serial Communication Interface (SCI) with two pins (or two additional GPIO lines)
• Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines)
2 56F801 Technical Data
For More Information On This Product,
Go to: www.freescale.com


Part Number F801FA60
Description DSP56F801FA60
Maker Motorola
Total Page 30 Pages
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