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NXP Semiconductors Electronic Components Datasheet

74VHC02-Q100 Datasheet

Quad 2-input NOR gate

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74VHC02-Q100 pdf
74VHC02-Q100; 74VHCT02-Q100
Quad 2-input NOR gate
Rev. 1 — 15 November 2013
Product data sheet
1. General description
The 74VHC02-Q100; 74VHCT02-Q100 are high-speed Si-gate CMOS devices and are
pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance
with JEDEC standard No. 7-A.
The 74VHC02-Q100; 74VHCT02-Q100 provide a quad 2-input NOR function.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accept voltages higher than VCC
Input levels:
The 74VHC02-Q100 operates with CMOS input level
The 74VHCT02-Q100 operates with TTL input level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74VHC02D-Q100 40 C to +125 C SO14
74VHCT02D-Q100
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74VHC02PW-Q100 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1
74VHCT02PW-Q100
body width 4.4 mm
74VHC02BQ-Q100 40 C to +125 C
74VHCT02BQ-Q100
DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1
very thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm


NXP Semiconductors Electronic Components Datasheet

74VHC02-Q100 Datasheet

Quad 2-input NOR gate

No Preview Available !

74VHC02-Q100 pdf
NXP Semiconductors
4. Functional diagram
74VHC02-Q100; 74VHCT02-Q100
Quad 2-input NOR gate
2 1A
3 1B
5 2A
6 2B
8 3A
9 3B
11 4A
12 4B
1Y 1
2Y 4
3Y 10
4Y 13
mna216
Fig 1. Logic symbol
2
1
3
1
5
1
6
4
8
1
9
10
11
1
12
13
001aah084
Fig 2. IEC logic symbol
5. Pinning information
5.1 Pinning
A
Y
B
mna215
Fig 3. Logic diagram (one gate)
9+&4
9+&74
< 
$ 
% 
< 
$ 
% 
*1' 
 9&&
 <
 %
 $
 <
 %
 $
DDD
Fig 4. Pin configuration SO14 and TSSOP14
9+&4
9+&74
WHUPLQDO
LQGH[DUHD
$ 
% 
< 
$ 
% 
*1' 
 <
 %
 $
 <
 %
DDD
7UDQVSDUHQWWRSYLHZ
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as a
supply pin or input.
Fig 5. Pin configuration DHVQFN14
74VHC_VHCT02_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 November 2013
© NXP B.V. 2013. All rights reserved.
2 of 15


Part Number 74VHC02-Q100
Description Quad 2-input NOR gate
Maker NXP
Total Page 15 Pages
PDF Download
74VHC02-Q100 pdf
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