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National Semiconductor Electronic Components Datasheet

DS99R104 Datasheet

(DS99R103 / DS99R104) DC-Balanced 24-Bit LVDS Serializer and Deserializer

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DS99R104 pdf
April 2007
DS99R103/DS99R104
3-40MHz DC-Balanced 24-Bit LVDS Serializer and
Deserializer
General Description
The DS99R103/104 Chipset translates a 24-bit parallel bus
into a fully transparent data/control LVDS serial stream with
embedded clock information. This single serial stream sim-
plifies transferring a 24-bit bus over PCB traces and cable by
eliminating the skew problems between parallel data and
clock paths. It saves system cost by narrowing data paths that
in turn reduce PCB layers, cable width, and connector size
and pins.
The DS99R103/104 incorporates LVDS signaling on the high-
speed I/O. LVDS provides a low power and low noise envi-
ronment for reliably transferring data over a serial transmis-
sion path. By optimizing the serializer output edge rate for the
operating frequency range EMI is further reduced.
In addition the device features pre-emphasis to boost signals
over longer distances using lossy cables. Internal DC bal-
anced encoding/decoding is used to support AC-Coupled
interconnects.
Features
3 MHz–40 MHz clock embedded and DC-Balancing 24:1
www.DataSheet4U.com and 1:24 data transmissions
Capable to drive shielded twisted-pair cable
User selectable clock edge for parallel data on both
Transmitter and Receiver
Internal DC Balancing encode/decode – Supports AC-
coupling interface with no external coding required
Individual power-down controls for both Transmitter and
Receiver
Embedded clock CDR (clock and data recovery) on
Receiver and no external source of reference clock
needed
All codes RDL (random data lock) to support hot-pluggable
applications
LOCK output flag to ensure data integrity at Receiver side
Balanced TSETUP/THOLD between RCLK and RDATA on
Receiver side
PTO (progressive turn-on) LVCMOS outputs to reduce
EMI and minimize SSO effects
All LVCMOS inputs and control pins have internal
pulldown
On-chip filters for PLLs on Transmitter and Receiver
Integrated 100Ω (±20%) termination in Receiver input
4 mA Receiver output drive
48-pin TQFP and 48-pin LLP packages
Pure CMOS .35 μm process
Power supply range 3.3V ± 10%
Temperature range −40°C to +85°C
8 kV HBM ESD structure
Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2007 National Semiconductor Corporation 202080
20208001
www.national.com


National Semiconductor Electronic Components Datasheet

DS99R104 Datasheet

(DS99R103 / DS99R104) DC-Balanced 24-Bit LVDS Serializer and Deserializer

No Preview Available !

DS99R104 pdf
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VDD)
LVCMOS/LVTTL Input Voltage
LVCMOS/LVTTL Output Voltage
LVDS Receiver Input Voltage
−0.3V to +4V
−0.3V to (VDD +0.3V)
−0.3V to (VDD +0.3V)
−0.3V to 3.9V
LVDS Driver Output Voltage
−0.3V to 3.9V
LVDS Output Short Circuit Duration
10 ms
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Lead Temperature
(Soldering, 4 seconds)
+260°C
Maximum Package Power Dissipation Capacity Package
De-rating:
48L TQFP
DS99R103
1/θJA °C/W above +25°C
 θJA
 θJC
DS99R104
45.8 (4L*); 75.4 (2L*) °C/W
21.0°C/W
 θJA
 θJC
45.4 (4L*); 75.0 (2L*)°C/W
21.1°C/W
48L LLP
DS99R103
 θJA
 θJC
DS99R104
 θJA
 θJC
ESD Rating (HBM)
1/θJA °C/W above +25°C
28 (4L*); 79.1 (2L*) °C/W
3.7°C/W
28 (4L*); 79.1 (2L*)°C/W
3.71°C/W
*JEDEC
±8 kV
Recommended Operating
Conditions
Supply Voltage (VDD)
Operating Free Air
Temperature (TA)
Clock Rate
Supply Noise
Min Nom Max
3.0 3.3 3.6
−40 +25 +85
3 40
±100
Units
V
°C
MHz
mVP-P
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
LVCMOS/LVTTL DC SPECIFICATIONS
VIH High Level Voltage
VIL Low Level Input Voltage
VCL Input Clamp Voltage
ICL = −18 mA
(Note 7)
IIN Input Current
VIN = 0V or 3.6V
VOH High Level Output Voltage IOH = −4 mA
VOL Low Level Output Voltage IOL = +4 mA
IOS Output Short Circuit Current VOUT = 0V
(Note 7)
IOZ TRI-STATE® Output Current RPWDNB, REN = 0V
VOUT = 0V or 2.4V
Pin/Freq.
Min Typ Max Units
Tx: DIN[23:0], TCLK,
TPWDNB, DEN, TRFB,
DCAOFF, DCBOFF,
VODSEL
Rx: RPWDNB, RRFB,
REN
Tx: DIN[23:0], TCLK,
TPWDNB, DEN, TRFB,
DCAOFF, DCBOFF,
VODSEL
Rx: RPWDNB, RRFB,
REN
Rx: ROUT[23:0], RCLK,
LOCK
2.0 1.5
GND 1.5
−0.8
−10 ±1
−20 ±5
2.3 3.0
GND 0.33
VDD
0.8
−1.5
+10
+20
VDD
0.5
V
V
V
µA
µA
V
V
−40 −70 −110 mA
Rx: ROUT[23:0], RCLK,
LOCK
−30 ±0.4 +30
µA
www.national.com
2


Part Number DS99R104
Description (DS99R103 / DS99R104) DC-Balanced 24-Bit LVDS Serializer and Deserializer
Maker National Semiconductor
Total Page 22 Pages
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