2.5V/3.3V, 5 Gb/s Multi Level
Clock/Data Input to CML
Driver / Receiver / Buffer/
Translator with Internal
The NB4L16M is a differential driver/receiver/buffer/translator
which can accept LVPECL, LVDS, CML, HSTL, LVCMOS/LVTTL
and produce 400 mV CML output. The device is capable of receiving,
buffering, and translating a clock or data signal that is as small as
75 mV operating up to 3.5 GHz or 5.0 Gb/s, respectively. As such, it is
ideal for SONET, GigE, Fiber Channel and backplane applications
(see Table 6 and Figures 20, 21 22, and 23).
Differential inputs incorporate internal 50 W termination resistors
and accept LVPECL (Positive ECL), LVTTL/LVCMOS, CML, HSTL
or LVDS. The differential 16 mA CML output provides matching
internal 50 W termination, and 400 mV output swing when externally
receiver terminated, 50 W to VCC (see Figure 19). These features
provide transmission line termination on chip, at the receiver and
driver end, eliminating any use of additional external components.
The VBB, an internally generated voltage supply, is available to this
device only. For single−ended input configuration, the unused
complementary differential input is connected to VBB as a switching
reference voltage. The VBB reference output can be used also to
re−bias capacitor coupled differential or single−ended output signals.
For the capacitor coupled input signals, VBB should be connected to
the VTD pin and bypassed to ground with a 0.01 mF capacitor. When
not used VBB should be left open.
This device is housed in a 3x3 mm 16 pin QFN package.
Application notes, models, and support documentation are available at
• Maximum Input Clock Frequency up to 3.5 GHz
• Maximum Input Data Rate up to 5.0 Gb/s
• < 0.7 ps Maximum Clock RMS Jitter
• < 10 ps Maximum Data Dependent Jitter at 2.5 Gb/s
• 220 ps Typical Propagation Delay
• 60 ps Typical Rise and Fall Times
• CML Output with Operating Range:
VCC = 2.375 V to 3.6 V with VEE = 0 V
• CML Output Level (400 mV Peak−to−Peak Output),
Differential Output Only
• 50 W Internal Input and Output Termination Resistors
• Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
• Pb−Free Packages are Available
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Figure 1. Functional Block Diagram
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
February, 2006 − Rev. 1
Publication Order Number: