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Power Integrations
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CHY100 Datasheet Preview

CHY100 Datasheet

Charger Interface Physical Layer IC

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CHY100 pdf
CHY100
ChiPhyFamily
Charger Interface Physical Layer IC
Product Highlights
Fully supports Quick Charge 2.0 specification
Class A: 5 V, 9 V, and 12 V output voltage
Class B: 5 V, 9 V, 12 V, and 20 V output voltage
USB battery charging specification revision 1.2 compatible
Automatic USB DCP shorting D+ to D- line
Default 5 V mode operation
Supports TOPSwitch and TinySwitch
Very low power consumption
Below 1 mW at 5 V output
Fail safe operation
Adjacent pin-to-pin short-circuit fault
Open circuit pin fault
Typical Applications
Battery chargers for smart phones, tablets, netbooks, digital
cameras, and bluetooth accessories
USB power output ports
Description
CHY100 is a low-cost USB high-voltage dedicated charging port
(HVDCP) interface IC for the Quick Charge 2.0 specification. It
incorporates all necessary functions to add Quick Charge 2.0
capability to Power Integrations’ switcher ICs such as TOPSwitch
or TinySwitch and other solutions employing traditional feedback
schemes.
CHY100 supports the full output voltage range of either Class A
or Class B. Optionally Class B can be inhibited for protecting the
battery charger from accidental damage.
CHY100 automatically detects whether a connected Powered
Device (PD) is Quick Charge 2.0 capable before enabling output
voltage adjustment. If a PD not compliant to Quick Charge 2.0 is
detected the CHY100 disables output voltage adjustment to
ensure safe operation with legacy 5 V only USB PDs.
VOUT
D+
D-
GND
Feedback
Network
BP
V3 D+
V2 CHY100 D-
U1
V1 R
GND
Figure 1. Typical Application Schematic.
PI-6988-071713
Figure 2. Package Option.
SO-8 (D Package)
www.powerint.com
This Product is Covered by Patents and/or Pending Patent Applications.
March 2014



Power Integrations
Power Integrations

CHY100 Datasheet Preview

CHY100 Datasheet

Charger Interface Physical Layer IC

No Preview Available !

CHY100 pdf
CHY100
BYPASS
(BP)
6V
3.9 V
+
BANDGAP
GND
OUTPUT
INHIBIT
+
2V
+
0.325 V
REFERENCE
(R)
D+
V3
V2 N3
V1 N2
N1
Figure 3. Functional Block Diagram.
CONTROL
LOGIC
(LOOKUP
TABLE)
S SET Q
R CLR Q
N5 D-
+
0.325 V
19.58 k
+
2V
GROUND
N4 (GND)
PI-7009-071513
Pin Functional Description
GROUND (GND) Pin
Ground.
V1 Pin
Open Drain input of output voltage adjustment switch.
Active for 9 V, 12 V, and 20 V output setting.
V2 Pin
Open Drain input of output voltage adjustment switch.
Active for 12 V, and 20 V output setting.
V3 Pin
Open Drain input of output voltage adjustment switch.
Active for 20 V output setting.
BYPASS (BP) Pin
Connection point for an external bypass capacitor for the
internally generated supply voltage.
REFERENCE (R) Pin
Connected to internal band-gap reference. Provides reference
current through connected resistor.
DATA LINE D+ Pin
USB D+ data line input.
DATA LINE D- Pin
USB D- data line input.
D Package (SO-8)
GND 1
V1 2
V2 3
V3 4
8 BP
7R
6 D+
5 D-
Figure 4. Pin Configuration.
PI-6987-071213
2
Rev. C 03/14
www.powerint.com


Part Number CHY100
Description Charger Interface Physical Layer IC
Maker Power Integrations
Total Page 6 Pages
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