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Ramtron Corporation
Ramtron Corporation

VRS51L3074 Datasheet Preview

VRS51L3074 Datasheet

FRAM-enhanced high performance 8051-based microcontroller coupled

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VRS51L3074
9 SPI Interface
The SPI interface of the VRS51L3074’s provides
numerous enhancements compared to other vendor
offerings. The SPI interface’s key features include:
Supports four standard SPI modes (clock
phase/polarity)
Operates in master and slave modes
Automatic control of up to four chip select lines
Configurable transaction size (1 to 32 bits)
Transaction size of >32 bits is possible
Double Rx and TX data buffers
Configurable MSB or LSB first transaction
Generation frame select/load signals
FIGURE 14: SPI INTERFACE OVERVIEW
Before the SPI can be accessed it must first be
enabled by setting the SPIEN bit of the PERIPHEN1
register to 1.
9.1 SPI Control Registers
The SPICTRL register controls the operating modes of
the SPI interface in master mode.
TABLE 97:SPI CONTROL REGISTER - SPICTRL SFR C1H
7 65 4 3 2
R/W
R/W
R/W
R/W
R/W
R/W
0 00 0 0
0
1
R/W
0
0
R/W
1
Bit Mnemonic Description
7 SPICLK[2:0] SPI Communication Speed (Master Mode)
000 = Sys Clk / 2 ( / 8 if SPISLOW = 1)
001 = Sys Clk / 4 ( / 16 if SPISLOW = 1)
010 = Sys Clk / 8 ( / 32 if SPISLOW = 1)
011 = Sys Clk / 16 ( / 64 if SPISLOW = 1)
100 = Sys Clk / 32 ( / 128 if SPISLOW = 1)
101 = Sys Clk / 64 ( / 256 if SPISLOW = 1)
110 = Sys Clk / 128 ( / 512 if SPISLOW = 1)
111 = Sys Clk / 256 ( / 1024 if SPISLOW = 1)
4
SPICS[1:0]
SPI Active Chip Select Line (Master Mode)
00 = CS0 is active
01 = CS1 is active
10 = CS2 is active
11 = CS3 is active
2
SPICLKPH
SPI Clock Phase
0 = SD0 output on rising edge and SDI
sampling on falling edge
1= SD0 output on falling edge and SDI sampling
on rising edge
1 SPICLKPOL SPI Clock Polarity
0 = SCK stays at 0 when SPI is inactive
1 = SCK stays at 1 when SPI is inactive
0 SPIMASTER SPI Master Mode Enable
0 = SPI operates in slave mode
1 = SPI operate in master mode (default)
When the SPIMASTER bit is set to 1, the SPI interface
operates in master mode. This is the default operating
mode of the VRS51L3074 SPI interface after reset.
9.2 Setting Up Clock Phase and Polarity
The clock phase and polarity is controlled by the
SPICLKPH and SPICLKPOL bits, respectively. The
following diagrams show the communication timing
associated with the clock phase and polarity.
SPI Mode 0:
FIGURE 15: SPI MODE 0
SPI MODE 0: SPICKPOL =0,SPICKPH =1 (Normal Mode Shown)
CSX
SCK
SDO
MSB
SDI
*Arrows indicate the edge where the data acquisition occurs
LSB
www.ramtron.com
page 51 of 105



Ramtron Corporation
Ramtron Corporation

VRS51L3074 Datasheet Preview

VRS51L3074 Datasheet

FRAM-enhanced high performance 8051-based microcontroller coupled

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VRS51L3074 pdf
www.DataSheet4U.com
VRS51L3074
SPI Mode 1:
FIGURE 16: SPI MODE 1
SPI MODE 1: SPICKPOL =0,SPICKPH =0 (Normal Mode Shown)
CSX
SCK
SDO
SDI
MSB
LSB
*Arrows indicate the edge where the data acquisition occurs
SPI Mode 2:
FIGURE 17: SPI MODE 2
SPI MODE 2: SPICKPOL =1,SPICKPH =1 (Normal Mode Shown)
CSX
SCK
SDO
MSB
SDI
LSB
*Arrows indicate the edge where the data acquisition occurs
SPI Mode 3:
FIGURE 18: SPI MODE 3
SPI MODE 3: SPICKPOL =1,SPICKPH =0 (Normal Mode Shown)
CSX
SCK
SDO
SDI
MSB
*Arrows indicate the edge where the data acquisition occurs
LSB
9.3 Defining active chip select line
As previously mentioned, only one chip select line is
activated when communicating with an external SPI
slave device. The SPICS bits of the SPICTRL register
are used to select which CS line will be activated
during the transfer.
Note that with the exception of the CS0 line, the
SPICSEN bit of the PERIPHEN1 register must be set
to 1 in order for the SPI be able to control the SPI CS
lines.
9.4 Setting the SPI Communication
Speed (Master Mode)
In master mode, the SPI interface communication
speed is adjustable from “system clock /2” down to
“system clock / 1024”. Slower communication speeds
can be useful for interfacing with slower devices or to
adjust the communication speed to specific bus
conditions.
The SPICLK SFR register and the SPISLOW bit of the
of the SPICONFIG SFR register control the SPI
communication speed.
The SPI communication speed in master mode can be
calculated using the following formula:
SPI speed =
Sys Clk
[ 2(SPICLK[2:0] +1) x 4SPISLOW ]
Where:
o Sys Clk = Processor operating clock
o SPISLOW = can be either 0 or 1
o SPICLK[2:0] = from 0 to 7
The following tables provide example setting for SPI
communication speeds with various system clock and
SPICLK[2:0] and SPISLOW bit settings.
TABLE 98:SPI COMMUNICATION SPEED EXAMPLE (SPISLOW = 0)
SPICLK
000
001
010
Com Speed
@ 40MHz
20 MHz
10 MHz
5 MHz
Com Speed
@ 22.18MHz
11.05 MHz
5.53 MHz
2.76 MHz
Com Speed
@ 4MHz
2 MHz
1 MHz
500 kHz
011
2.5 MHz
1.38 MHz
250 kHz
100
1.25 MHz
691.2 kHz
125 kHz
101
625 kHz
345.6 kHz
62.5 kHz
110
312.5 kHz
172.8 kHz
31.3 kHz
111
156.3 kHz
86.4 kHz
15.6 kHz
TABLE 99:SPI COMMUNICATION SPEED EXAMPLE (SPISLOW = 1)
SPICLK
000
001
010
011
100
101
110
111
Com Speed
@ 40MHz
5 MHz
2.50 MHz
1.25 MHz
625 kHz
312.5 kHz
156.3 kHz
78.1 kHz
39.1 kHz
Com Speed
@ 22.18MHz
2.76 MHz
1.38 MHz
691.2 kHz
345.6 kHz
172.8 kHz
86.4 kHz
43.2 kHz
21.6 kHz
Com Speed
@ 4MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.3 kHz
15.6 kHz
7.8 kHz
3.9 kHz
www.ramtron.com
page 52 of 105


Part Number VRS51L3074
Description FRAM-enhanced high performance 8051-based microcontroller coupled
Maker Ramtron Corporation
Total Page 30 Pages
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