Parallel-Load 8-bit Shift Register
The LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in
access to each stage is made available by eight individual direct data inputs that are enabled by a low level at the shift /
load input. These registers also feature gated clock inputs and complementary outputs from the eighth bit. All inputs
are diode-clamped to minimize transmission-line effects, thereby simplifying system design.
Clocking is accomplished through a 2-input positive-NOR gate, permitting one input to be used as a clock-inhibit
function. Holding either of the clock inputs high inhibits clocking and holding either clock input low with the shift /
load input high enables the other clock input. The clock-inhibit input should be changed to the high level only while the
clock input is high. Parallel loading is inhibited as long as the shift / load input is high. Data at the parallel inputs are
loaded directly into the register on a high-to-low transition of the shift / load input independently of the levels of the
clock, clock inhibit, or serial inputs.
• Ordering Information
HD74LS165AFPEL SOP-16 pin (JEITA)
Note: Please consult the sales office for the above package availability.
EL (2,000 pcs/reel)
Inputs G 5
Output QH 7
9 Output QH
Rev.3.00, Jul.15.2005, page 1 of 7