SDM-09120 925-960 MHz 130W Power Amp Module
Pin # Function
LDMOS FET Q1 and Q2 gate bias. VGSTH 3.0 to 5.0 VDC. See Notes 2, 3 and 4
Module Topside ground.
3 RF Input Internally DC blocked
LDMOS FET Q3 and Q4 gate bias. VGSTH 3.0 to 5.0 VDC. See Notes 2, 3 and 4
6 VD2 LDMOS FET Q3 and Q4 drain bias. See Note 1.
8 RF Output Internally DC blocked
LDMOS FET Q1 and Q2 drain bias. See Note 1.
Baseplate provides electrical ground and a thermal transfer path for the device. Proper mounting assures
optimal performance and the highest reliability. See Sirenza applications note AN-054 Detailed Installation Instructions for
Simplified Device Schematic
1 +3V DC to +6 V DC
5 +3V DC to +6 V DC
Absolute Maximum Ratings
Drain Voltage (VDD)
RF Input Power
Load Impedance for Continuous Operation
Control (Gate) Voltage, VDD = 0 VDC
Output Device Channel Temperature
Operating Temperature Range
Storage Temperature Range
Operation of this device beyond any one of these limits may cause per-
manent damage. For reliable continuous operation see typical setup val-
ues specified in the table on page one.
Internal RF decoupling is included on all bias leads. No addi-
tional bypass elements are required, however some applica-
tions may require energy storage on the VD leads to
accommodate modulated signals.
Gate voltage must be applied to VGS leads simultaneously with
or after application of drain voltage to prevent potentially
destructive oscillations. Bias voltages should never be applied
to a module unless it is properly terminated on both input and
The required VGS corresponding to a specific IDQ will vary from
module to module and may differ between VGS1 and VGS2 on
the same module by as much as ±0.10 volts due to the normal
die-to-die variation in threshold voltage for LDMOS transistors.
The threshold voltage (VGSTH) of LDMOS transistors varies with
device temperature. External temperature compensation may
be required. See Sirenza application notes AN-067 LDMOS
Bias Temperature Compensation.
This module was designed to have it's leads hand
soldered to an adjacent PCB. The maximum soldering iron tip
temperature should not exceed 700° C, and the soldering iron
tip should not be in direct contact with the lead for longer than
10 seconds. Refer to app note AN054 (www.sirenza.com) for
further installation instructions.
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
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