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SEP02G72E2BF2SA-30R Datasheet Preview

SEP02G72E2BF2SA-30R Datasheet

SDRAM registered DIMM

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SEP02G72E2BF2SA-30R pdf
Data Sheet
Rev.1.0 23.11.2010
2GB DDR2 SDRAM registered DIMM
240 Pin RDIMM
SEP02G72E2BF2SA-30R
2GB PC2-5300 in FBGA Technology
RoHS compliant
Options:
Data Rate / Latency
DDR2 533 MTs / CL4
DDR2 667 MT/s / CL5
Marking
-37
-30
Module Density
2048MB with 18 dies and 2 ranks
Standard Grade (TA)
(TC)
0°C to 70°C
0°C to 85°C
Environmental Requirements:
Operating temperature (TAMBIENT)
Standard Grade
Operating Humidity
0°C to 70°C
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Features:
240-pin 72-bit DDR2 registered Dual-In-Line Double Data
Rate Synchronous DRAM Module for server applications
Module organization: dual rank 256M x 72
VDD = 1.8V ±0.1V, VDDQ 1.8V ±0.1V
1.8V I/O ( SSTL_18 compatible)
Serial Presence Detect with EEPROM
Supports ECC error detection and correction
JEDEC compatible DDR2 PLL/Register component with
parity bit support for address and control bus
Gold-contact pad
This module family is fully pin and functional compatible
to JEDEC. (see www.jedec.org)
The pcb and all components are manufactured according
to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
DDR2 SDRAM component Samsung K4T1G084QF
128Mx8 DDR2 SDRAM in FBGA-60 package
Four bit prefetch architecture
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency 1 tCK
Programmable burst length: 4 or 8
Adjustable data-output drive strength
On-die termination (ODT)
DLL to align DQ and DQS transitions with CK
Figure: mechanical dimensions1
Swissbit AG
Industriestrasse 4
CH 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
1if no tolerances specified ± 0.15mm
www.swissbit.com
eMail: info@swissbit.com
Page 1
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Swissbit
Swissbit

SEP02G72E2BF2SA-30R Datasheet Preview

SEP02G72E2BF2SA-30R Datasheet

SDRAM registered DIMM

No Preview Available !

SEP02G72E2BF2SA-30R pdf
Data Sheet
Rev.1.0 23.11.2010
This Swissbit module is an industry standard 240-pin 8-byte DDR2 registered SDRAM Dual-In-line Memory
Module (RDIMM) which is organized as x72 high speed CMOS memory arrays. All control and address signals
are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive
loading to the system bus, but adds one cycle to the SDRAM timing. De-coupling capacitors, stub resistors,
calibration resistors and termination resistors are mounted on the PCB board. The module uses double data rate
architecture to achieve high-speed operation. DDR2 SDRAM modules operate from a differential clock (CK and
CK#). READ and WRITE accesses to a DDR2 SDRAM module is burst-oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed sequence. The burst length is
either four or eight locations. An auto precharge function can be enabled to provide a self-timed row precharge
that is initiated at the end of a burst access. The DDR2 SDRAM devices have a multibank architecture which
allows a concurrent operation that is providing a high effective bandwidth. A self refresh mode is provided and a
power-saving “power-down” mode. All inputs and all full drive-strength outputs are SSTL_18 compatible.
The DDR2 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
using the standard I2C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the DIMM manufacturer (Swissbit) to identify the module type, the module’s organization and several
timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
256M x 72bit
DDR2 SDRAMs used
18 x 128M x 8bit (1024Mbit)
Row
Addr.
14
Device Bank
Select
Column
Addr.
Refresh
Module
Bank Select
BA0, BA1, BA2 10
8k S0#, S1#
Module Dimensions
in mm
133.33 (long) x 30(high) x 4 [max] (thickness)
Timing Parameters
Part Number
SEP02G72E2BF2SA-37R
SEP02G72E2BF2SA-30R
Module Density
2048 MB
2048 MB
Transfer Rate
4.2 GB/s
5.3 GB/s
Clock Cycle/Data bit
rate
3.7ns/533MT/s
3.0ns/667MT/s
Latency
4-4-4
5-5-5
Pin Name
A0 A13
BA0 BA2
DQ0 DQ63
CB0 CB7
DM0 DM8
DQS0 DQS8
DQS0# - DQS8#
RAS#
CAS#
WE#
CKE0 CKE1
CK0 CK1
CK0# - CK1#
S0#, S1#
Reset#
Address Inputs
Bank Address Inputs
Data Input / Output
Data check bits Input / Output
Input Data Mask
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Input, positive line
Clock Input, negative line
Chip Select
Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal
can be used during power-up to ensure that CKE is LOW and DQs are High-Z.
Swissbit AG
Industriestrasse 4
CH 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 2
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Part Number SEP02G72E2BF2SA-30R
Description SDRAM registered DIMM
Maker Swissbit
Total Page 14 Pages
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