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XPLA3 Datasheet

CPLD

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XPLA3 pdf
APPLICATION NOTE
0
CoolRunner™ XPLA3 CPLD
DS012 (v1.1) March 3, 2000
0 14* Advance Product Specification
Features
• Fast Zero Power (FZP™) design technique provides
ultra-low power and very high speed
• Innovative XPLA3 architecture combines high speed
with extreme flexibility
• Based on industry's first TotalCMOS™ PLD - both
CMOS design and process technologies
• Advanced 0.35µ five metal layer E2CMOS process
- 1,000 erase/program cycles guaranteed
- 20 years data retention guaranteed
• 3V, In-System Programmable (ISP) using JTAG IEEE
1149.1 interface
- Full Boundary Scan Test (IEEE 1149.1)
• Ultra-low static power of less than 100 µA
• Simple deterministic timing model
• Support for complex asynchronous clocking
- 16 product term clocks and four local control term
clocks per logic block
- Four global clocks and one universal control term
clock per device
www.DataSheet4U.com Excellent pin retention during design changes
• 5V tolerant I/O pins
• Input register set up time of 1.7 ns
• Logic expandable to 48 product terms
• High-speed pin-to-pin delays of 5.0 ns
• Slew rate control per macrocell
• 100% routable
• Security bit prevents unauthorized access
• Supports hot-plugging capability
• Design entry/verification using Xilinx or industry
standard CAE tools
• Innovative Control Term structure provides:
- Asynchronous macrocell clocking
- Asynchronous macrocell register preset/reset
- Clock enable control per macrocell
• Four output enable controls per logic block
• Foldback NAND for synthesis optimization
• Global 3-state which facilitates "bed of nails" testing
• Available in Chip-scale BGA, and QFP packages
• Commercial and extended voltage industrial grades
• Pin compatible with existing CoolRunner low-power
family devices
Family Overview
The CoolRunner XPLA3 (eXtended Programmable Logic
Array) family of CPLDs is targeted for low power systems
that include portable, handheld, and power sensitive appli-
cations. Each member of the XPLA3 family includes Fast
Zero Power (FZP) design technology that combines low
power and high speed. With this design technique, the
XPLA3 family offers true pin-to-pin speeds of 5.0 ns, while
simultaneously delivering power that is less than 100 µA at
standby without the need for "turbo bits" or other power
down schemes. By replacing conventional sense amplifier
methods for implementing product terms (a technique that
has been used in PLDs since the bipolar era) with a cas-
caded chain of pure CMOS gates, the dynamic power is
also substantially lower than any competing CPLD. Cool-
Runner devices are the only TotalCMOS PLDs, as they use
both a CMOS process technology and the patented full
CMOS FZP design technique.
To the original XPLA architecture, XPLA3 adds a direct
input register path, multiple clocks (both dedicated and
product term generated), and both reset and preset for
each macrocell, with a full PLA structure. These enhance-
ments deliver high speed coupled with very flexible logic
allocation which results in the ability to make design
changes without changing pinout. The XPLA3 logic block
includes a pool of 48 product terms that can be allocated to
any macrocell in the logic block. Logic that is common to
multiple macrocells can be placed on a single PLA product
term and shared, effectively increasing design density.
XPLA3 CPLDs are supported by WebPACK from Xilinx and
industry standard CAE tools (Cadence/OrCAD, Exemplar
Logic, Mentor, Synopsys, Viewlogic, andd Synplicity), using
text (ABEL, VHDL, Verilog) and schematic capture design
entry. Design verification uses industry standard simulators
for functional and timing simulation. Development is sup-
ported on personal computer, Sparc, and HP platforms.
Device fitting uses Xilinx developed tools including
WebFITTER.
The XPLA3 family features also include industry-standard,
IEEE 1149.1, JTAG interface through which In-System Pro-
gramming (ISP) and reprogramming of the device can
DS012 (v1.1) March 3, 2000
www.xilinx.com
1-800-255-7778
1



Xilinx
Xilinx

XPLA3 Datasheet Preview

XPLA3 Datasheet

CPLD

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XPLA3 pdf
R
occur. The XPLA3 CPLD is electrically reprogrammable
using industry standard device programmers from vendors
such as Data I/O, BP Microsystems, and SMS.
XPLA3 Architecture
Figure 1 shows a high-level block diagram of a 128 macro-
cell device implementing the XPLA3 architecture. The
XPLA3 architecture consists of logic blocks that are inter-
connected by a Zero-power Interconnect Array (ZIA). The
ZIA is a virtual crosspoint switch. Each logic block has 36
inputs from the ZIA and 16 macrocells.
From this point of view, this architecture looks like many
other CPLD architectures. What makes the XPLA3 family
unique is logic allocation inside each logic block and the
design technique used to implement these logic blocks.
Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic
block contains a PLA array that generates control terms,
CoolRunnerXPLA3 CPLD
clock terms, and logic cells. There are 36 pairs of true and
complement inputs from the ZIA that feed the 48 product
terms in the array. Within the 48 P-terms there are eight
local control terms (LCT[0:7]) available as control inputs to
each macrocell for use as asynchronous clocks, resets,
presets and output enables. The other P-terms serve as
additional single inputs into each macrocell.
There are eight foldback NAND P-terms that are available
for ease of fitting and pin locking. Sixteen product terms are
coupled with the associated programmable OR gate into
the VFM (Variable Function Multiplexer). The VFM
increases logic optimization by implementing any two input
logic funtion before entering the macrocell (see Figure 3).
Each macrocell can support combinatorial or registered
inputs, preset and reset on a per macrocell basis and con-
figurable D, T registers, or latch function. If a macrocell
needs more product terms, it simply gets the additional
product terms from the PLA array.
MC0
MC1
LOGIC
I/O BLOCK
MC15
MC0
MC1
LOGIC
I/O BLOCK
MC15
MC0
MC1
LOGIC
I/O BLOCK
MC15
MC0
MC1
LOGIC
I/O BLOCK
MC15
36 36
16 16
16 16
36 36
16 16
16 16
ZIA
36 36
16 16
16 16
36 36
16 16
16 16
Figure 1: Xilinx XPLA3 CPLD Architecture
DS012 (v1.1) March 3, 2000
www.xilinx.com
1-800-255-7778
LOGIC
BLOCK
MC0
MC1
MC15
I/O
LOGIC
BLOCK
MC0
MC1
MC15
I/O
LOGIC
BLOCK
MC0
MC1
MC15
I/O
LOGIC
BLOCK
MC0
MC1
MC15
I/O
ds012_01_121399
2


Part Number XPLA3
Description CPLD
Maker Xilinx
Total Page 11 Pages
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XPLA3 pdf
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